LH28F320S5HNS-ZP Sharp Electronics, LH28F320S5HNS-ZP Datasheet - Page 14

• Manufacturer Part Number: LH28F320S5HNS-ZP
• Manufacturer: Sharp Electronics

Specifications of LH28F320S5HNS-ZP

• Cell Type: NOR
• Density: 32Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 22/21Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: -40C to 85C
• Package Type: SSOP
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 4M/2M
• Supply Current: 75mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Compliant

NOTES:
1. BUS operations are defined in Table 3 and Table 3.1.
2. X=Any valid address within the device.
3. SRD=Data read from status register. See Table 14 for a description of the status register bits.
4. Following the Read Identifier Codes command, read operations access manufacturer, device and block status
5. If the block is locked, WP# must be at V
6. Either 40H or 10H are recognized by the WSM as the byte write setup.
7. A block lock-bit can be set while WP# is V
8. WP# must be at V
9. Following the Third Bus Cycle, inputs the write address and write data of ’N’ times. Finally, input the confirm
10. Commands other than those shown above are reserved by SHARP for future device implementations and
Read Array/Reset
Read Identifier Codes
Query
Read Status Register
Clear Status Register
Block Erase Setup/Confirm
Full Chip Erase Setup/Confirm
Word/Byte Write Setup/Write
Alternate Word/Byte Write
Setup/Write
Multi Word/Byte Write
Setup/Confirm
Block Erase and (Multi)
Word/byte Write Suspend
Confirm and Block Erase and
(Multi) Word/byte Write Resume
Block Lock-Bit Set Setup/Confirm
Block Lock-Bit Reset
Setup/Confirm
STS Configuration
Level-Mode for Erase and Write
(RY/BY# Mode)
STS Configuration
Pulse-Mode for Erase
STS Configuration
Pulse-Mode for Write
STS Configuration
Pulse-Mode for Erase and Write
IA=Identifier Code Address: see Figure 4.
QA=Query Offset Address.
BA=Address within the block being erased or locked.
WA=Address of memory location to be written.
WD=Data to be written at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high
first).
ID=Data read from identifier codes.
QD=Data read from query database.
codes. See Section 4.2 for read identifier code data.
to issue a block erase or (multi) word/byte write to a locked block while RP# is V
lock-bits.
command ’D0H’.
should not be used.
Command
IH
to clear block lock-bits. The clear block lock-bits operation simultaneously clears all block
Bus Cycles Notes
Req’d
Table 4. Command Definitions
≥2
≥2
≥4
1
2
1
2
2
2
2
1
1
2
2
2
2
2
2
IH
to enable block erase or (multi) word/byte write operations. Attempts
IH
.
LHF32KZP
5,6
5,6
4
5
9
5
5
7
8
Oper
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
First Bus Cycle
(1)
Addr
WA
WA
WA
BA
BA
X
X
X
X
X
X
X
X
X
X
X
X
X
(10)
(2)
Data
D0H
FFH
E8H
B0H
B8H
B8H
B8H
B8H
90H
98H
70H
50H
20H
30H
40H
10H
60H
60H
(3)
IH
.
Oper
Read
Read
Read
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
Second Bus Cycle
(1)
Addr
WA
WA
WA
QA
BA
BA
IA
X
X
X
X
X
X
X
(2)
Rev. 1.6
Data
SRD
D0H
D0H
D0H
01H
00H
01H
02H
03H
WD
WD
N-1
QD
ID
(3)
11