E28F400B5B80 Intel, E28F400B5B80 Datasheet - Page 25

• Manufacturer Part Number: E28F400B5B80
• Manufacturer: Intel

Specifications of E28F400B5B80

• Density: 4Mb
• Access Time (max): 80ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

4.1.3
When CE# is at a logic-high level (V
device is not programming or erasing, the memory
enters in standby mode, which disables much of the
device’s circuitry and substantially reduces power
consumption. Outputs (DQ
placed in a high-impedance state independent of
the status of the OE# signal. When CE# is at logic-
high level during program or erase operations, the
device will continue to perform the operation and
consume corresponding active power until the
operation is completed.
4.1.4
The 5 Volt Boot Block Flash family supports a low
typical I
off all circuits to save power. This mode is activated
by the RP# pin when it is at a logic-low (GND
0.2 V). Note: BYTE# pin must be at CMOS levels to
meet the I
During read modes, the RP# pin going low de-
selects the memory and places the output drivers in
a high impedance state. Recovery from the deep
power-down state, requires a minimum access time
of t
to the device will clear the status register.
During an program or erase operation, RP# going
low for time t
location’s memory contents will no longer valid and
additional timing must be met. See Section 3.1.5
and Figure 15 and Table 10 for additional
information.
4.2
The device protects against accidental block
erasure or programming during power transitions.
Power supply sequencing is not required, so either
V
the read mode after power-up, but the system must
drop CE# low or present an address to receive valid
data at the outputs.
A system designer must guard against spurious
writes when V
is active. Since both WE# and CE# must be low for
a command write, driving either signal to V
inhibit writes to the device. Additionally, alteration of
memory can only occur after successful completion
of a two-step command sequences. The device is
also disabled until RP# is brought to V
PP
PHQV
PRELIMINARY
or V
CCD
. RP# transitions to V
CC
Power-Up/Down Operation
CCD
STANDBY POWER
DEEP POWER-DOWN MODE
in deep power-down mode, which turns
can power-up first. The CUI defaults to
PLPH
specification.
CC
voltages are above V
will abort the operation, but the
0
–DQ
IL
, or turning power off
15
or DQ
IH
LKO
IH
, regardless
0
), and the
–DQ
and V
IH
7
) are
will
PP
of the state of its control inputs. By holding the
device in reset (RP# connected to system
PowerGood) during power-up/down, invalid bus
conditions during power-up can be masked,
providing yet another level of memory protection.
4.2.1
Using RP# properly during system reset is
important with automated program/erase devices
because the system expects to read from the flash
memory when it comes out of reset. If a CPU reset
occurs without a flash memory reset, proper CPU
initialization would not occur because the flash
memory may in a mode other than Read Array.
Intel’s
initialization following a system reset by connecting
the RP# pin to the same RESET# signal that resets
the system CPU.
4.3
4.3.1
Flash memory’s switching characteristics require
careful decoupling methods. System designers
should consider three supply current issues:
standby current levels (I
(I
rising edges of CE#.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection
will suppress these transient voltage peaks. Each
flash device should have a 0.1 µF ceramic
capacitor connected between V
between V
inherently low-inductance capacitors should be
placed as close as possible to the package leads.
4.3.2
In-system updates to the flash memory requires
special consideration of the V
by the printed circuit board designer. Since the V
pin supplies the current for programming and
erasing, it should have similar trace widths and
layout considerations as given to the V
supply trace. Adequate V
decoupling capacitors placed adjacent to the
component, will decrease spikes and overshoots.
CCR
), and transient peaks produced by falling and
28F200B5, 28F004/400B5, 28F800B5
Flash
Board Design
RP# CONNECTED TO SYSTEM
RESET
POWER SUPPLY DECOUPLING
V
BOARDS
PP
PP
TRACE ON PRINTED CIRCUIT
and GND. These high-frequency,
memories
CCS
PP
), active current levels
allow
PP
supply traces, and
power supply trace
CC
and GND, and
proper
CC
power
CPU
25
PP