PA28F400B5T80 Intel, PA28F400B5T80 Datasheet - Page 6

• Manufacturer Part Number: PA28F400B5T80
• Manufacturer: Intel

Specifications of PA28F400B5T80

• Density: 4Mb
• Access Time (max): 80ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 19/18Bit
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8/16Bit
• Number Of Words: 512K/256K
• Supply Current: 65mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

28F200B5, 28F004/400B5, 28F800B5
SmartVoltage technology enables fast factory
programming and low-power designs. Specifically
designed for 5 V systems, 5 Volt Boot Block Flash
components support read operations at 5 V V
and internally configure to program/erase at 5 V or
12 V. The 12 V V
program and erase performance which will increase
your factory throughput. With the 5 V V
V
design. In addition, the dedicated V
complete data protection when V
The memory array is asymmetrically divided into
blocks
accommodate microprocessors that boot from the
top (denoted by -T suffix) or the bottom (-B suffix)
of the memory map. The blocks include a
hardware-lockable boot block (16,384 bytes), two
parameter blocks (8,192 bytes each) and main
blocks (one block of 98,304 bytes and additional
block(s) of 131,072 bytes). See Figures 4–7 for
memory maps. Each block can be independently
erased
commercial
extended temperature. At automotive temperature,
each parameter block can be independently erased
and programmed 30,000 times, and each main and
boot block 1,000 times. Unlike erase operations,
which
simultaneously, each byte or word in the flash
memory can be programmed independently of other
memory locations.
The
complete code security for the kernel code required
for system initialization. Locking and unlocking of
the boot block is controlled by WP# and/or RP#
(see Section 3.3 for details).
The system processor interfaces to the flash device
through a Command User Interface (CUI), using
valid command sequences to initiate device
automation. An internal Write State Machine (WSM)
automatically executes the algorithms and timings
necessary for program and erase operations. The
Status Register (SR) indicates the status of the
WSM and whether it successfully completed the
desired program or erase operation.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
6
CC
and V
hardware-lockable
erase
in
and
PP
an
can be tied together for a simple 5 V
temperature
programmed
all
asymmetrical
PP
locations
option renders the fastest
CCR
boot
or
current is 1 mA.
100,000
PP
10,000
within
block
architecture
V
PP
PPLK
PP
times
pin gives
times
a
.
provides
option,
block
CC
to
at
at
When CE# and RP# pins are at V
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (t
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
from RP#-high until writes to the CUI are
recognized. See Section 4.2.
The deep power-down mode can also be used as a
device reset, allowing the flash to be reset along
with the rest of the system. For example, when the
flash memory powers-up, it automatically defaults
to the read array mode, but during a warm system
reset, where power continues uninterrupted to the
system components, the flash memory could
remain in a non-read mode, such as erase.
Consequently, the system Reset signal should be
tied to RP# to reset the memory to normal read
mode upon activation of the Reset signal. This also
provides protection against unwanted command
writes due to invalid system bus conditions during
system reset or power-up/down sequences.
These devices are configurable at power-up for
either byte-wide or word-wide input/output using the
BYTE# pin. Please see Table 2 for a detailed
description of BYTE# operations, especially the
usage of the DQ
These 5 Volt Boot Block Flash memory products
are available in the 44-lead PSOP (Plastic Small
Outline
compatible, and the 48-lead TSOP (Thin Small
Outline Package, 1.2 mm thick) as shown in
Figure 1, and 2, respectively.
2.0
This section describes the pinout and block
architecture of the device family.
2.1
The pin descriptions table details the usage of each
of the device pins.
PRODUCT DESCRIPTION
Pin Descriptions
Package),
15
/A
–1
pin.
which
PRELIMINARY
is
ROM/EPROM-
CC
PHQV
, the
PHEL
) is
)