PA28F008SC-85 Intel, PA28F008SC-85 Datasheet - Page 12

• Manufacturer Part Number: PA28F008SC-85
• Manufacturer: Intel

Specifications of PA28F008SC-85

• Density: 8Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
2.0
The byte-wide SmartVoltage FlashFile memories
include an on-chip WSM to manage block erase,
program, and lock-bit configuration functions. It
allows for: 100% TTL-level control inputs, fixed
power supplies during block erasure, program, and
lock-bit
overhead with RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see Bus Operations), the
device defaults to read array mode. Manipulation of
external memory control pins allow array read,
standby, and output disable operations.
Status register and identifier codes can be
accessed through the CUI independent of the V
voltage. High voltage on V
block erasure, program, and lock-bit configuration.
All functions associated with altering memory
contents—block
configuration, status, and identifier codes—are
accessed via the CUI and verified through the
status register.
Commands are written using standard micro-
processor write timings. The CUI contents serve as
input to the WSM that controls block erase,
program, and lock-bit configuration operations. The
internal algorithms are regulated by the WSM,
including pulse repetition, internal verification, and
margining of data. Addresses and data are
internally latched during write cycles. Writing the
appropriate command outputs array data, accesses
the identifier codes, or outputs status register data.
Interface software that initiates and polls progress
of block erase, program, and lock-bit configuration
can be stored in any block. This code is copied to
and executed from system RAM during flash
memory updates. After successful completion,
reads are again possible via the Read Array
command. Block erase suspend allows system
software to suspend a block erase to read or write
data from any other block. Program suspend allows
system software to suspend a program to read data
from any other flash memory array location.
12
PRINCIPLES OF OPERATION
configuration,
erase,
and
PP
program,
minimal
enables successful
processor
lock-bit
PP
1DFFFF
1CFFFF
1BFFFF
1AFFFF
0DFFFF
0CFFFF
0BFFFF
0AFFFF
1FFFFF
1EFFFF
0FFFFF
0EFFFF
19FFFF
18FFFF
17FFFF
16FFFF
15FFFF
14FFFF
13FFFF
12FFFF
11FFFF
10FFFF
09FFFF
08FFFF
07FFFF
06FFFF
05FFFF
04FFFF
03FFFF
02FFFF
01FFFF
00FFFF
1F0000
1E0000
1D0000
1C0000
1B0000
1A0000
0F0000
0E0000
0D0000
0C0000
0B0000
0A0000
190000
180000
170000
160000
150000
140000
130000
120000
110000
100000
090000
080000
070000
060000
050000
040000
030000
020000
010000
000000
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
64-Kbyte Block
Figure 5. Memory Map
PRELIMINARY
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
4-Mbit
8-Mbit
16-Mbit