PA28F008SC-85 Intel, PA28F008SC-85 Datasheet - Page 6

• Manufacturer Part Number: PA28F008SC-85
• Manufacturer: Intel

Specifications of PA28F008SC-85

• Density: 8Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

BYTE-WIDE SmartVoltage FlashFile™ MEMORY FAMILY
A block erase operation erases one of the device’s
64-Kbyte
(5 V V
Each block can be independently erased 100,000
times (1.6 million block erases per device). A block
erase suspend operation allows system software to
suspend block erase to read data from or write data
to any other block.
Data is programmed in byte increments typically
within 6
suspend operation permits system software to read
data or execute code from any other flash memory
array location.
To protect programmed data, each block can be
locked. This block locking mechanism uses a
combination of bits, block lock-bits and a master
lock-bit, to lock and unlock individual blocks. The
block lock-bits gate block erase and program
operations, while the master lock-bit gates block
lock-bit configuration operations. Lock-bit config-
uration operations (Set Block Lock-Bit, Set Master
Lock-Bit, and Clear Block Lock-Bits commands) set
and clear lock-bits.
The status register and RY/BY# output indicate
whether or not the device is busy executing or
ready for a new command. Polling the status
register, system software retrieves WSM feedback.
The RY/BY# output gives an additional indicator of
WSM activity by providing a hardware status signal.
Like the status register, RY/BY#-low indicates that
6
CC
, 12 V V
s (5 V V
blocks
PP
), independent of other blocks.
typically
CC
, 12 V V
within
PP
). A program
1
second
the WSM is performing a block erase, program, or
lock-bit
indicates that the WSM is ready for a new
command, block erase is suspended (and program
is inactive), program is suspended, or the device is
in deep power-down mode.
The Automatic Power Savings (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
5 V V
When CE# and RP# pins are at V
component enters a CMOS standby mode. Driving
RP# to GND enables a deep power-down mode
which significantly reduces power consumption,
provides write protection, resets the device, and
clears the status register. A reset time (t
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
from RP#-high until writes to the CUI are
recognized.
1.3
The family of devices is available in 40-lead TSOP
(Thin Small Outline Package, 1.2 mm thick) and
44-lead PSOP (Plastic Small Outline Package) and
40-bump
only). Pinouts are shown in Figures 2, 3 and 4.
CC
.
Pinout and Pin Description
configuration
BGA* CSP (28F008SC and 28F016SC
PRELIMINARY
operation.
CCR
current is 1 mA at
RY/BY#-high
CC
PHQV
, the
PHEL
) is
)