E28F016SA-100 Intel, E28F016SA-100 Datasheet
E28F016SA-100
Specifications of E28F016SA-100
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E28F016SA-100 Summary of contents
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... SSOP Package Intel’s 28F016SA 16-Mbit FlashFile™ memory is a revolutionary architecture which is the ideal choice for designing embedded direct-execute code and mass storage data/file flash memory systems. With innovative capabilities, low-power, extended temperature operation and high read/program performance, the 28F016SA enables the design of truly mobile, high-performance communications and computing products ...
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... Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. ...
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INTRODUCTION .............................................5 1.1 Product Overview.........................................5 2.0 DEVICE PINOUT .............................................6 2.1 Lead Descriptions ........................................8 3.0 MEMORY MAPS ...........................................12 3.1 Extended Status Register Memory Map .....13 4.0 BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS .............14 4.1 Bus Operations for Word-Wide Mode ...
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REVISION HISTORY Number -001 Original Version -002 Added 56-Lead SSOP Package Separated AC Reading Timing Specs t Reads Modified Device Nomenclature Added Ordering Information Added Page Buffer Typical Program Performance numbers Added Typical Erase Suspend Latencies For I (Deep ...
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... INTRODUCTION The documentation of the Intel 28F016SA memory device includes this datasheet, a detailed user’s manual, and a number of application notes, all of which are referenced at the end of this datasheet. The datasheet is intended to give an overview of the chip feature-set and of the operating AC/DC specifications. The 16-Mbit Flash Product Family User’ ...
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... RY/BY# pins together in a multiple memory configuration such as a Resident Flash Array. Other configurations of the RY/BY# pin are enabled via special CUI commands and are described in detail in the 16-Mbit Flash Product Family User’s Manual. The 28F016SA also incorporates a dual chip-enable function with two input pins, CE ...
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DQ 8-15 Output Buffer Input Buffer Y Decoder Address Queue Latches X Decoder Address Counter Figure 1. 28F016SA Block Diagram Architectural Evolution Includes Page Buffers, Queue Registers and Extended Status Registers SEE NEW DESIGN RECOMMENDATIONS DQ 0-7 Output Input Input ...
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Lead Descriptions Symbol Type A INPUT BYTE-SELECT ADDRESS: Selects between high and low byte when the 0 device mode. This address is latched in x8 data programs. Not used in x16 mode (i.e., the A ...
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... There is a significant delay from 3/5# switching to valid data. V SUPPLY ERASE/PROGRAM POWER SUPPLY: For erasing memory array blocks PP or writing words/bytes/pages into the flash array. V SUPPLY DEVICE POWER SUPPLY (3.3V ± 10%, 5.0V ± 10%, 5.0V ± 5%): CC Do not leave any power pins floating. ...
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... GND GND NOTE: 56-Lead TSOP Mechanical Diagrams and Dimensions are shown at the end of this specification. Figure 2. TSOP Pinout Configuration 10 SEE NEW DESIGN RECOMMENDATIONS E28F016SA 45 56-LEAD TSOP PINOUT 1 TOP VIEW 28F016SV 28F032SA WP# WP# WP# WE# WE# WE# OE# OE# OE# RY/BY# RY/BY# RY/BY GND GND GND ...
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3/5# 3/ ...
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MEMORY MAPS A [20-0] 1FFFFF 1F0000 1EFFFF 1E0000 1DFFFF 1D0000 1CFFFF 1C0000 1BFFFF 1B0000 1AFFFF 1A0000 19FFFF 190000 18FFFF 180000 17FFFF 170000 16FFFF 160000 15FFFF 150000 14FFFF 140000 13FFFF 130000 12FFFF 120000 11FFFF 110000 10FFFF 100000 0FFFFF 0F0000 ...
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Extended Status Register Memory Map x8 MODE A[20-0] 1F0006H RESERVED 1F0005H GSR 1F0004H RESERVED 1F0003H BSR 31 1F0002H RESERVED 1F0001H RESERVED 1F0000H . . . 010002H RESERVED 000006H RESERVED 000005H GSR 000004H RESERVED 000003H BSR 0 000002H RESERVED 000001H ...
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BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS 4.1 Bus Operations for Word-Wide Mode (BYTE Mode Notes RP# Read 1,2 Output Disable 1,6 Standby 1,6 Deep Power-Down 1 Manufacturer ...
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... PA = Program Address X = Don’t Care NOTES: 1. Following the Intelligent Identifier command, two read operations access the manufacturer and device signature code s. 2. The CSR is automatically available after device enters data program, block erase, or suspend operations. 3. Clears CSR.3, CSR.4 and CSR.5. Also clears GSR.5 and all BSR.5 and BSR.2 bits. ...
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... Write Single Load to Page Write Buffer Sequential Load to x8 4,6,10 Write Page Buffer x16 4,5,6,10 Write Page Buffer Write to x8 3,4,9,10 Write Flash x16 4,5,10 Write Two-Byte Program x8 3 Write Lock Block/Confirm Write Upload Status 2 Write Bits/Confirm Upload Device Write Information ...
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... These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY function. 9. Program address, PA, is the destination address in the flash array which must match the source address in the Page Buffer. Refer to the 16-Mbit Flash Product Family User’s Manual . ...
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Compatible Status Register WSMS ESS CSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy CSR.6 = ERASE-SUSPEND STATUS 1 = Erase Suspended 0 = Erase In Progress/Completed CSR.5 = ERASE STATUS ...
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Global Status Register WSMS OSS DOS GSR.7 = WRITE STATE MACHINE STATUS 1 = Ready 0 = Busy GSR.6 = OPERATION SUSPEND STATUS 1 = Operation Suspended 0 = Operation in Progress/Completed GSR.5 = DEVICE OPERATION ...
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Block Status Register BS BLS BOS BSR.7 = BLOCK STATUS 1 = Ready 0 = Busy BSR.6 = BLOCK-LOCK STATUS 1 = Block Unlocked for Program/Erase 0 = Block Locked for Program/Erase BSR.5 = BLOCK ...
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... SEE NEW DESIGN RECOMMENDATIONS NOTICE: This is a production datasheet. The specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. * WARNING: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent damage. These are stress ratings only. Operation beyond the “ ...
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Capacitance For a 3.3V System: Symbol Parameter Capacitance Looking into Address/Control Pin Capacitance Looking into an C OUT Output Pin Load Capacitance Driven by C LOAD Outputs for Timing Specifications Equivalent Testing Load Circuit For ...
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Timing Nomenclature All 3.3V system timings are measured from where signals cross 1.5V. For 5.0V systems use the standard JEDEC cross point definitions. Each timing parameter consists of five characters. Some common examples are defined below time(t) ...
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INPUT 0.8 0.45 AC test inputs are driven at V (2.4 VTTL) for a Logic “1” and V OH (2.0 VTTL) and V (0.8 VTTL). Output timing ends Figure 7. Transient Input/Output Reference Waveform ...
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Transmission Line From Output under Test Total Capacitance = 100 pF Figure 9. Transient Equivalent Testing Load Circuit (V 2 From Output under Test Total Capacitance = 50 pF Figure 10. Transient Equivalent ...
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DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE 3.3V ±10 +70 C, – + 3/5# = Pin Set High for 3.3V Operations Temp Sym Parameter Notes I Input ...
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DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued 3.3V ±10 +70 C, – + 3/5# = Pin Set High for 3.3V Operations Temp Sym Parameter Notes I 1 ...
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DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued 3.3V ± 10 +70 C, – + 3/5# = Pin Set High for 3.3V Operations Temp Sym Parameter Notes ...
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DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0V ± 10%, 5.0V ± 5 +70 C, – + 3/5# Pin Set Low for 5V Operations Temp Sym Parameter Notes ...
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DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued 5.0V ± 10%, 5.0V ± 5 +70 C, – + 3/5# Pin Set Low for 5V Operations Temp Sym ...
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DC Characteristics: COMMERCIAL AND EXTENDED TEMPERATURE (Continued 5.0V ± 10%, 5.0V ± 5%, + 3/5# Pin Set Low for 5V Operations Temp Sym Parameter Notes ...
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AC Characteristics–Read Only Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 3.3V ± 10 +70 C, – + Temp Speed Sym Parameter V CC Load Notes t Read Cycle ...
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AC Characteristics–Read Only Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0V ± 10%, 5.0V ± 5 +70 C. – + Temp Speed Sym Parameter V CC Load Notes t ...
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For Extended Status Register Reads Temp Load Versions V ± ± 10% CC Sym Parameter Notes t Address 3,4 AVEL Setup to CE# Going Low t Address 3,4 AVGL Setup to OE# Going Low NOTES: ...
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V IH ADDRESSES (A) ADDRESSES STABLE (1) CEx# ( AVEL AVGL OE# ( WE# ( GLQX ELQX HIGH Z DATA ...
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V IH ADDRESSES ( (1) CEx #( AVFL AVEL OE# ( ELFL t AVGL V IH BYTE# ( ...
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Power-Up and Reset Timings: COMMERCIAL/EXTENDED TEMPERATURE V Power-Up CC RP# t YHPH (P) 3/5# (Y) 3. (3V,5V PHEL3 Address (A) t AVQV Data Valid 3.3V Outputs (Q) t PHQV Figure 14. V ...
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AC Characteristics for WE#–Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 3.3V ± 10 +70 C, – + Sym Parameter t Write Cycle Time AVAV t ...
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AC Characteristics for WE#–Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0V ±10%, 5.0V ± 5 +70 C, – + Temp Versions V ± ...
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AC Characteristics for WE#–Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0V ±10%, 5.0V ± 5 +70 C, – + Temp Versions V ± ...
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... Word/byte program operations are typically performed with 1 programming pulse. 6. Address and data are latched on the rising edge of WE# for all command write operations. 7. This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel sales office for more information. WRITE VALID ADDRESS DEEP WRITE DATA-WRITE OR & ...
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AC Characteristics for CE#–Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 3.3V ±10 + Sym Parameter t Write Cycle Time AVAV t V ...
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AC Characteristics for CE#–Controlled Command Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0 to 10% , 5.0 ± 5 0°C to +70 C, –40° Temp Versions V ± ...
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... Word/byte program operations are typically performed with 1 programming pulse. 6. Address and data are latched on the rising edge of CE# for all command write operations. 7. This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel sales office for more information. 44 SEE NEW DESIGN RECOMMENDATIONS ...
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WRITE VALID ADDRESS DEEP WRITE DATA-WRITE OR & DATA (DATA-WRITE) OR POWER-DOWN ERASE SETUP COMMAND ERASE CONFIRM COMMAND V IH ADDRESSES ( NOTE AVAV AVEH V IH ADDRESSES ( NOTE ...
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AC Characteristics for Page Buffer Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 3.3V ± 10 +70 C, – + Sym Parameter t Write Cycle Time AVAV t ...
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AC Characteristics for Page Buffer Write Operations: COMMERCIAL AND EXTENDED TEMPERATURE V = 5.0V ± 10%, 5.0V ± 5 +70 C, – + Temp Sym Parameter Speed V CC ...
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V IH CEx#( ELWL V IH WE# ( AVWL ADDRESSES ( HIGH Z DATA (D/ Figure 17. Page Buffer Write Timing Waveforms (Loading Data to ...
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... This assumes using the full Page Buffer to data program to the flash memory (256 bytes or 128 words). 5. Typical 1,000,000 cycle performance assumes the application uses block retirement techniques. 6. This information will be available in a technical paper. Please call Intel’s Application Hotline or your local Intel Sales office for more information. SEE NEW DESIGN RECOMMENDATIONS = +70 C ...
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DERATING CURVES Figure 18. I vs. Frequency (V = 5.5V) for x16 Operation Figure 19. I during Block Erase CC 50 SEE NEW DESIGN RECOMMENDATIONS 290489-16.eps Figure 20. I vs. Frequency ( ...
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Figure 22. Access Time (t Figure 23. I during Word Write Operation PP SEE NEW DESIGN RECOMMENDATIONS ) vs. Output Loading ACC 290489-25.eps Figure 24. I during Page Buffer Write PP Operation 28F016SA 290489-24.eps 290489-26 51 ...
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MECHANICAL SPECIFICATIONS FOR TSOP Figure 25. Mechanical Specifications of the 28F016SA 56-Lead TSOP Type 1 Package Family: Thin Small Outline Package Symbol Minimum 0.965 2 b 0.100 c 0.115 D 18. ...
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MECHANICAL SPECIFICATIONS FOR SSOP Figure 26. Mechanical Specifications of the 56-Lead SSOP Package Family: Shrink Small Outline Package Symbol Minimum A A1 0.47 A2 1.18 B 0.25 C 0.13 D 23.40 E 13.10 e ...
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... Load 1 E28F016SA-070 E28F016SA-120 2 E28F016SA-100 E28F016SA-150 3 DA28F016SA-070 DA28F016SA-120 4 DA28F016SA-100 DA28F016SA-150 5 DT28F016SA-100 DT28F016SA-150 54 SEE NEW DESIGN RECOMMENDATIONS ACCESS SPEED 70 ns 100 ns 100 ns Valid Combinations = 3.3V ± 10 5.0V ± 10%, CC 100 pF Load E28F016SA-080 E28F016SA-100 DA28F016SA-080 DA28F016SA-100 DT28F016SA-150 0 0489_18 V = 5.0V ± 5 Load E28F016SA-070 DA28F016SA-070 DT28F016SA-150 ...
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... FLASHBuilder Design Resource Tool NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers shou ld contact their local Intel or distribution sales office. 2. Visit Intel’s World Wide Web home page at http://www.Intel.com for technical documentation and tools. ...