E28F016SA-100 Intel, E28F016SA-100 Datasheet - Page 17

• Manufacturer Part Number: E28F016SA-100
• Manufacturer: Intel

Specifications of E28F016SA-100

• Density: 16Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 11.4 to 12.6V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 60mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. BCL = 00H corresponds to a byte count of 1. Similarly, WCL = 00H corresponds to a word count of 1.
11. To ensure that the 28F016SA’s power consumption during sleep mode reaches the deep power-down current level, the
12. The upper byte of the data bus (DQ
SEE NEW DESIGN RECOMMENDATIONS
RA can be the GSR address or any BSR address. See Figures 5 and 6 for Extended Status Register Memory Maps.
Upon device power-up, all BSR lock-bits come up locked. The Upload Status Bits command must be written to reflect the
actual lock-bit status.
A
The A
BCH/WCH must be at 00H for this product because of the 256-byte (128-word) Page Buffer size and to avoid writing the
Page Buffer contents into more than one 256-byte segment within an array block. They are simply shown for future Page
Buffer expandability.
In x16 mode, only the lower byte DQ
PBA and PD (whose count is given in cycles 2 and 3) are supplied starting in the fourth cycle, which is not shown.
This command allows the user to swap between available Page Buffers (0 or 1).
These commands reconfigure the RY/BY# output to one of two pulse-modes or enable and disable the RY/ B Y# function.
Program address, PA, is the destination address in the flash array which must match the source address in the Page
Buffer. Refer to the 16-Mbit Flash Product Family User’s Manual .
system also needs to de-select the chip by taking either or both CE
0
is automatically complemented to load the second byte of data. BYTE# must be at V
0
value determines which WD/BC is supplied first: A
8–15
0–7
) during command writes is a “Don’t Care” in x16 operation of the device.
is used for WCL and WCH. The upper byte DQ
0
= 0 looks at the WDL/BCL, A
0
# or CE
1
# high.
8–15
IL
0
.
= 1 looks at the WDH/BCH.
is a don’t care.
28F016SA
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