MT4C4M4E8DJ-5 Micron Technology Inc, MT4C4M4E8DJ-5 Datasheet - Page 2

• Manufacturer Part Number: MT4C4M4E8DJ-5
• Manufacturer: Micron Technology Inc
• Type: EDO DRAMr

Specifications of MT4C4M4E8DJ-5

• Density: 16Mb
• Access Time (max): 25ns
• Operating Supply Voltage (typ): 5V
• Package Type: SOJ
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Supply Current: 140mA
• Pin Count: 26
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Supplier Unconfirmed

GENERAL DESCRIPTION (continued)
cycles, OE# must be taken HIGH to disable the data outputs
prior to applying input data. If a LATE WRITE or READ-
MODIFY-WRITE is attempted while keeping OE# LOW, no
WRITE will occur, and the data outputs will drive read data
from the accessed location.
through four pins using common I/O, and pin direction is
controlled by WE# and OE#.
order to retain stored data.
PAGE ACCESS
WRITE or READ-MODIFY-WRITE) within a row-
address-defined page boundary. The page cycle is always
initiated with a row address strobed in by RAS#, followed
by a column address strobed in by CAS#. Additional
columns may be accessed by providing valid column
addresses, strobing CAS# and holding RAS# LOW, thus
executing faster memory cycles. Returning RAS# HIGH
terminates the page mode of operation, i.e., closes the page.
4 Meg x 4 EDO DRAM
D47.p65 – Rev. 6/98
ADDR
RAS#
CAS#
OE#
DQ
The four data inputs and the four data outputs are routed
The 4 Meg x 4 DRAM must be refreshed periodically in
Page operations allow faster data operations (READ,
V
V
V
V
IOH
IOL
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
IH
IL
ROW
OPEN
COLUMN (A)
VALID DATA (A)
The DQs go back to
Low-Z if
t OD
t OES
t OE
t
OES is met.
OE# CONTROL OF DQs
VALID DATA (A)
COLUMN (B)
Figure 1
2
EDO PAGE MODE
which is an accelerated FAST-PAGE-MODE cycle. The
primary advantage of EDO is the availability of data-out
even after CAS# returns HIGH. EDO allows CAS# precharge
time (
This elimination of CAS# output control allows pipelined
READs.
the output buffers off (High-Z) with the rising edge of
CAS#. EDO-PAGE-MODE DRAMs operate like FAST-
PAGE-MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z (refer to
Figure 1). WE# can also perform the function of disabling
the output devices under certain conditions, as shown in
Figure 2.
OE# must be used to disable idle banks of DRAMs. Alterna-
VALID DATA (B)
The 4 Meg x 4 EDO DRAM provides EDO PAGE MODE,
FAST-PAGE-MODE DRAMs have traditionally turned
During an application, if the DQ outputs are wire OR’d,
t OD
The DQs remain High-Z
until the next CAS# cycle
if
t
t OEHC
CP) to occur without the output data going invalid.
t
OEHC is met.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
COLUMN (C)
VALID DATA (C)
The DQs remain High-Z
until the next CAS# cycle
if
t OEP
t
OEP is met.
t OD
EDO DRAM
4 MEG x 4
1998, Micron Technology, Inc.
COLUMN (D)
DON’T CARE
UNDEFINED
VALID DATA (D)