MT46V8M16TG-75 Micron Technology Inc, MT46V8M16TG-75 Datasheet - Page 66

• Manufacturer Part Number: MT46V8M16TG-75
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V8M16TG-75

• Organization: 8Mx16
• Density: 128Mb
• Address Bus: 14b
• Access Time (max): 750ps
• Maximum Clock Rate: 266MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 140mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Figure 38:
Figure 39:
PDF: 09005aef816fd013/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 128Mb DDR: Rev. F; Core DDR: Rev. A 4/07 EN
Nonconsecutive WRITE-to-WRITE
Random WRITE Cycles
Notes:
Notes:
t
DQSS (NOM)
COMMAND
COMMAND
1. DI b (or n) = data-in from column b (or column n).
2. Three subsequent elements of data-in are applied in the programmed order following DI b.
3. Three subsequent elements of data-in are applied in the programmed order following DI n.
4. An uninterrupted burst of 4 is shown.
5. Each WRITE command may be to any bank.
1. DI b (or x or n or a or g) = data-in from column b (or column x, or column n, or column a, or
2. b', x', n', a' or g' indicate the next data-in following DO b, DO x, DO n, DO a, or DO g,
3. Programmed BL = 2, BL = 4, or BL = 8 in cases shown.
4. Each WRITE command may be to any bank.
ADDRESS
ADDRESS
column g).
respectively.
DQS
DQS
CK#
DM
DQ
CK#
DM
DQ
CK
CK
WRITE
WRITE
Bank,
Col b
Bank,
Col b
T0
T0
t
DQSS (NOM)
t
DQSS
WRITE
Bank,
NOP
Col x
T1
DI
T1
DI
b
b
66
T1n
T1n
DI
b'
WRITE
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Bank,
NOP
Col n
T2
T2
DI
x
T2n
T2n
DI
x'
128Mb: x4, x8, x16 DDR SDRAM
WRITE
WRITE
Bank,
Col n
Bank,
T3
Col a
T3
DI
n
DON’T CARE
DON’T CARE
T3n
DI
n'
©2004 Micron Technology, Inc. All rights reserved.
WRITE
T4
Bank,
NOP
DI
Col g
T4
n
DI
a
TRANSITIONING DATA
TRANSITIONING DATA
T4n
T4n
DI
a'
Operations
T5
T5
NOP
NOP
DI
g
T5n
T5n
DI
g'