MC9S08GT16CFB Freescale Semiconductor, MC9S08GT16CFB Datasheet - Page 118
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MC9S08GT16CFB
Manufacturer Part Number
MC9S08GT16CFB
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC9S08GT16CFB.pdf
(290 pages)
Specifications of MC9S08GT16CFB
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
SCI/SPI
Program Memory Type
Flash
Program Memory Size
16KB
Total Internal Ram Size
1KB
# I/os (max)
36
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.08V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
44
Package Type
PQFP
Lead Free Status / Rohs Status
Not Compliant
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Internal Clock Generator (ICG) Module
7.5.1
RANGE — Frequency Range Select
REFS — External Reference Select
CLKS — Clock Mode Select
The CLKS bits are writable at any time, unless the first write after a reset was CLKS = 0X, the CLKS bits
cannot be written to 1X until after the next reset (because the EXTAL pin was not reserved).
118
1. This bit is reserved for Freescale Semiconductor internal use only. Any write operations to this register should write
The RANGE bit controls the oscillator, reference divider, and FLL loop prescaler multiplication factor
(P). It selects one of two reference frequency ranges for the ICG. The RANGE bit is write-once after
a reset. The RANGE bit only has an effect in FLL engaged external and FLL bypassed external modes.
The REFS bit controls the external reference clock source for ICGERCLK. The REFS bit is write-once
after a reset.
The CLKS bits control the clock mode according to
requested, it will not be selected until ERCS = 1. If the ICG enters off mode, the CLKS bits will remain
unchanged.Writes to the CLKS bits will not take effect if a previous write is not complete.
a 0 to this bit.
1 = Oscillator configured for high frequency range. FLL loop prescale factor P is 1.
0 = Oscillator configured for low frequency range. FLL loop prescale factor P is 64.
1 = Oscillator using crystal or resonator requested.
0 = External clock requested.
ICG Control Register 1 (ICGC1)
Reset:
Read:
Write:
Bit 7
0
0
CLKS[1:0]
Figure 7-12. ICG Control Register 1 (ICGC1)
00
01
10
11
= Unimplemented or Reserved
RANGE
MC9S08GB/GT Data Sheet, Rev. 2.3
Figure 7-13. CLKS Clock Select
6
1
REFS
FLL bypassed, external reference
FLL engaged, external reference
FLL engaged, internal reference
5
0
Self-clocked
Clock Mode
Figure
4
0
CLKS
7-13. If FLL bypassed external is
3
0
OSCSTEN
2
1
Freescale Semiconductor
0
1
(1)
0
Bit 0
0
0
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