CY7C09199-6AC Cypress Semiconductor Corp, CY7C09199-6AC Datasheet - Page 16
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CY7C09199-6AC
Manufacturer Part Number
CY7C09199-6AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C09199-6AC.pdf
(19 pages)
Specifications of CY7C09199-6AC
Density
1.125Mb
Access Time (max)
15ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
52MHz
Operating Supply Voltage (typ)
5V
Address Bus
17b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
450mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
9b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
Read/Write and Enable Operation
Address Counter Control Operation
Notes:
Document #: 38-06039 Rev. *A
32. “X” = “Don’t Care,” “H” = V
33. ADS, CNTEN, CNTRST = “Don’t Care.”
34. OE is an asynchronous input signal.
35. When CE changes state in the pipelined mode, deselection and read happen in the following clock cycle.
36. CE
37. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
38. Counter operation is independent of CE
Address
OE
A
H
X
X
X
X
X
X
L
n
0
and OE = V
Previous
Address
A
A
CLK
X
X
IL
n
n
; C
X
E1
and R/W = V
IH
CLK
, “L” = V
Inputs
CE
H
X
L
L
L
IL
IH
ADS
.
0
.
H
H
X
L
0
and CE
CNTEN
1
.
H
X
X
L
[32, 33, 34]
CE
H
H
H
X
L
[32, 36, 37, 38]
1
CNTRST
H
H
H
L
R/W
X
X
H
X
L
D
D
D
D
out(n+1)
I/O
out(0)
out(n)
out(n)
Outputs
I/O
High-Z
High-Z
High-Z
Increment
D
D
0
OUT
Mode
Reset
Load
–I/O
Hold
IN
8
Counter Reset to Address 0
Address Load into Counter
External Address Blocked—Counter
Disabled
Counter Enabled—Internal Address
Generation
Deselected
Deselected
Write
Read
Outputs Disabled
[33]
CY7C09089/99
CY7C09189/99
Operation
[35]
[35]
Operation
Page 16 of 19
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