CY7C09199-6AC Cypress Semiconductor Corp, CY7C09199-6AC Datasheet - Page 9
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CY7C09199-6AC
Manufacturer Part Number
CY7C09199-6AC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CY7C09199-6AC.pdf
(19 pages)
Specifications of CY7C09199-6AC
Density
1.125Mb
Access Time (max)
15ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
52MHz
Operating Supply Voltage (typ)
5V
Address Bus
17b
Package Type
TQFP
Operating Temp Range
0C to 70C
Number Of Ports
2
Supply Current
450mA
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
100
Word Size
9b
Number Of Words
128K
Lead Free Status / Rohs Status
Not Compliant
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = V
Read Cycle for Pipelined Operation (FT/PIPE = V
Notes:
Document #: 38-06039 Rev. *A
14. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
15. ADS = V
16. The output is disabled (high-impedance state) by CE
17. Addresses do not have to be accessed sequentially since ADS = V
ADDRESS
ADDRESS
DATA
DATA
IL
CLK
R/W
CE
CE
OUT
CLK
R/W
CE
CE
OE
, CNTEN and CNTRST = V
OUT
OE
0
1
0
1
t
t
t
t
t
t
SC
SW
SA
SC
SW
SA
A
A
n
n
t
t
t
t
HC
HW
HA
t
t
t
CH2
t
HC
HW
HA
CH1
IH
t
1 Latency
CKLZ
.
t
CD1
t
t
CYC2
CYC1
t
CKLZ
t
CL2
t
0
CL1
=V
IH
A
A
or CE
n+1
n+1
IH
IL
)
[14, 15, 16, 17]
1
)
t
Q
IL
DC
[14, 15, 16, 17]
= V
t
n
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
CD2
IL
following the next rising edge of the clock.
Q
A
n
A
n+2
n+2
Q
t
OHZ
n+1
t
DC
Q
t
t
t
SC
SC
t
OE
n+1
t
OLZ
OHZ
A
A
n+3
CY7C09089/99
CY7C09189/99
n+3
t
OLZ
Q
t
DC
n+2
t
t
HC
HC
t
OE
t
CKHZ
Page 9 of 19
Q
n+2
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