CY62146DV30LL-70BVI Cypress Semiconductor Corp, CY62146DV30LL-70BVI Datasheet

CY62146DV30LL-70BVI

Manufacturer Part Number
CY62146DV30LL-70BVI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY62146DV30LL-70BVI

Density
4Mb
Access Time (max)
70ns
Sync/async
Asynchronous
Architecture
Not Required
Clock Freq (max)
Not RequiredMHz
Operating Supply Voltage (typ)
3V
Address Bus
18b
Package Type
VFBGA
Operating Temp Range
-40C to 85C
Number Of Ports
1
Supply Current
15mA
Operating Supply Voltage (min)
2.2V
Operating Supply Voltage (max)
3.6V
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
48
Word Size
16b
Number Of Words
256K
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CY62146DV30LL-70BVI
Manufacturer:
CY
Quantity:
25
Part Number:
CY62146DV30LL-70BVI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Cypress Semiconductor Corporation
Document #: 38-05339 Rev. *A
Features
Functional Description
The CY62146DV30 is a high-performance CMOS static RAM
organized as 256K words by 16 bits. This device features ad-
vanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life™ (MoBL
applications such as cellular telephones. The device also has
Note:
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Pin-compatible with CY62146CV30
• Ultra-low active power
• Ultra low standby power
• Easy memory expansion with CE, and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered 48-ball BGA and 44-pin TSOPII
• Also available in Lead-free packages
Logic Block Diagram
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 8 mA @ f = f
A
A
A
A
A
A
A
A
A
A
A
10
3
1
0
9
7
6
5
4
2
8
[1]
COLUMN DECODER
max
DATA IN DRIVERS
3901 North First Street
RAM Array
) in portable
256K x 16
an automatic power-down feature that significantly reduces
power consumption. The device can also be put into standby
mode reducing power consumption by more than 99% when
deselected (CE HIGH). The input/output pins (I/O
I/O
(CE HIGH), outputs are disabled (OE HIGH), both Byte High
Enable and Byte Low Enable are disabled (BHE, BLE HIGH),
or during a write operation (CE LOW and WE LOW).
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O
written into the location specified on the address pins (A
through A
from I/O pins (I/O
specified on the address pins (A
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O
LOW, then data from memory will appear on I/O
the truth table at the back of this data sheet for a complete
description of read and write modes.
The CY62146DV30 is available in a 48-ball VFBGA, 44-pin
TSOPII packages.
4-Mbit (256K x 16) Static RAM
15
) are placed in a high-impedance state when: deselected
17
). If Byte High Enable (BHE) is LOW, then data
San Jose
8
through I/O
0
I/O
I/O
to I/O
,
CA 95134
0
8
–I/O
–I/O
BHE
WE
CE
OE
BLE
7
. If Byte High Enable (BHE) is
15
7
15
0
Revised February 2, 2005
) is written into the location
through A
CY62146DV30
0
17
through I/O
).
408-943-2600
8
to I/O
0
through
15
. See
7
), is
0
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CY62146DV30LL-70BVI Summary of contents

Page 1

... A 0 Note: 1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05339 Rev. *A 4-Mbit (256K x 16) Static RAM an automatic power-down feature that significantly reduces power consumption. The device can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH) ...

Page 2

... CY62146DV30LL CY62146DV30L 2.20V 3.0 CY62146DV30LL Notes pins are not internally connected on the die. 3. DNU pins have to be left floating or tied ensure proper application Pins H1, G2, and H6 in the BGA package are address expansion pins for 8 Mb, 16 Mb, and 32 Mb, respectively. ...

Page 3

... Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current...................................................... >200 mA Operating Range + 0.3V CC(MAX) Device CY62146DV30L Industrial –40°C to +85°C 2.20V to 3.60V + 0.3V CC(MAX) CY62146DV30LL CY62146DV30-45 CY62146DV30-55 [5] Min. Typ. Max. Min. Typ. = 2.20V 2.0 2 ...

Page 4

Capacitance (for all packages) Parameter Description C Input Capacitance IN C Output Capacitance OUT Thermal Resistance [9] Parameter Description Θ Thermal Resistance JA (Junction to Ambient) Θ Thermal Resistance JC (Junction to Case) AC Test Loads and Waveforms R1 ...

Page 5

Switching Characteristics Over the Operating Range Parameter Description Read Cycle t Read Cycle Time RC t Address to Data Valid AA t Data Hold from Address Change OHA t CE LOW to Data Valid ACE t OE LOW to Data ...

Page 6

Switching Waveforms Read Cycle 1 (Address Transition Controlled) ADDRESS DATA OUT PREVIOUS DATA VALID [17, 18] Read Cycle No. 2 (OE Controlled) ADDRESS CE t ACE OE BHE/BLE t LZOE t DBE t LZBE HIGH IMPEDANCE DATA OUT t LZCE ...

Page 7

Switching Waveforms (continued) [15, 19, 20] Write Cycle No. 1 (WE Controlled) ADDRESS BHE/BLE OE DATA I/O NOTE 21 t HZOE [15, 19, 20] Write Cycle No. 2 (CE Controlled) ADDRESS CE WE BHE/BLE OE DATA ...

Page 8

Switching Waveforms (continued) Write Cycle No. 3 (WE Controlled, OE LOW) ADDRESS CE BHE/BLE NOTE 21 DATAI/O t Write Cycle No. 4 (BHE/BLE Controlled, OE LOW) ADDRESS CE BHE/BLE DATA I/O NOTE 21 Document ...

Page 9

... Ordering Information Speed (ns) Ordering Code 45 CY62146DV30LL-45BVI CY62146DV30LL-45BVXI CY62146DV30LL-45ZSXI 55 CY62146DV30L-55BVI CY62146DV30L-55BVXI CY62146DV30LL-55BVI CY62146DV30LL-55BVXI CY62146DV30L-55ZSXI CY62146DV30LL-55ZSXI 70 CY62146DV30L-70BVI CY62146DV30L-70BVXI CY62146DV30LL-70BVI CY62146DV30LL-70BVXI CY62146DV30L-70ZSXI CY62146DV30LL-70ZSXI Document #: 38-05339 Rev. *A Inputs/Outputs X High Z Deselect/Power-Down High Z Output Disabled L Data Out (I/O –I/O ) Read Data Out (I/O –I/O ); Read O 7 I/O – ...

Page 10

... Document #: 38-05339 Rev. *A © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress ...

Page 11

Document History Page Document Title:CY62146DV30 MoBL Document Number: 38-05339 Orig. of REV. ECN NO. Issue Date Change ** 213251 See ECN *A 316039 See ECN Document #: 38-05339 Rev. *A ® 4-Mbit (256K x 16) Static RAM Description of Change ...

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