CY7C1347C-200AC Cypress Semiconductor Corp, CY7C1347C-200AC Datasheet

CY7C1347C-200AC

Manufacturer Part Number

CY7C1347C-200AC

Description

Manufacturer

Cypress Semiconductor Corp

Datasheet

1.CY7C1347C-200AC.pdf (24 pages)

Specifications of CY7C1347C-200AC

Density

4.5Mb

Access Time (max)

2.5ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

200MHz

Operating Supply Voltage (typ)

3.3V

Address Bus

18b

Package Type

TQFP

Operating Temp Range

0C to 70C

Number Of Ports

Supply Current

360mA

Operating Supply Voltage (min)

3.135V

Operating Supply Voltage (max)

3.6V

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

100

Word Size

36b

Number Of Words

128K

Lead Free Status / Rohs Status

Not Compliant

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Features

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced tri-

ple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

Selection Guide

Cypress Semiconductor Corporation

Maximum Access Time (ns)

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

• Fast access times: 2.5 and 3.5 ns

• Fast clock speed: 250, 225, 200, and 166 MHz

• 1-ns set-up time and hold time

• Fast OE access times: 2.5 ns and 3.5 ns

• Optimal for depth expansion (one cycle chip deselect

• 3.3V –5% and +10% power supply

• 3.3V or 2.5V I/O supply

• 5V tolerant inputs except I/Os

• Clamp diodes to V

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Three chip enables for depth expansion and address

• Address, data, and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst se-

• Automatic power-down for portable applications

• JTAG boundary scan

• JEDEC standard pinout

• Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid

to eliminate bus contention)

pipeline

quence)

Array) and 100-pin TQFP packages

at all inputs and outputs

256K x 18/128K x 36 Synchronous-Pipelined

•

3901 North First Street

7C1347C-250

71128DA36-4

71256DA18-4

7C1327C-250

450

2.5

The

GVT71256DA18

262,144x18 SRAM cells with advanced synchronous periph-

eral circuitry and a 2-bit counter for internal burst operation. All

synchronous inputs are gated by registers controlled by a pos-

itive-edge-triggered clock input (CLK). The synchronous in-

puts include all addresses, all data inputs, address-pipelining

Chip Enable (CE), depth-expansion Chip Enables (CE2 and

CE2), Burst Control Inputs (ADSC, ADSP , and ADV), Write

Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write

(GW).

Asynchronous inputs include the Output Enable (OE) and

Burst Mode Control (MODE). The data outputs (Q), enabled

by OE, are also asynchronous.

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate self-timed Write cycle. Write cycles can be one to

four bytes wide as controlled by the write control inputs. Indi-

vidual byte write allows individual byte to be written. BWa con-

trols DQa. BWb controls DQb. BWc controls DQc. BWd con-

trols DQd. BWa, BWb, BWc, and BWd can be active only with

BWE being LOW. GW being LOW causes all bytes to be writ-

ten. The x18 version only has 18 data inputs/outputs (DQa and

DQb) along with BWa and BWb (no BWc, BWd, DQc, and

DQd).

Four pins are used to implement JTAG test capabilities: Test

Mode Select (TMS), Test Data-in (TDI), Test Clock (TCK), and

Test Data-out (TDO). The JTAG circuitry is used to serially shift

data to and from the device. JTAG inputs use LVTTL/LVCMOS

levels to shift data during this testing mode of operation.

The

GVT71256DA18 operate from a +3.3V power supply. All inputs

and outputs are LVTTL compatible

71128DA36-4.4

71256DA18-4.4

7C1347C-225

7C1327C-225

CY7C1347C/GVT71128DA36

•

400

2.5

CY7C1347C/GVT71128DA36

CY7C1327C/GVT71256DA18

San Jose

SRAMs

7C1347C-200

71128DA36-5

7C1327C-200

71256DA18-5

•

CA 95134

360

2.5

integrate

Cache RAM

and

131,072x36

•

7C1347C-166

71128DA36-6

71256DA18-6

7C1327C-166

CYC7C1327C/

408-943-2600

CY7C1327C/

July 21, 2000

300

3.5

and

Related parts for CY7C1347C-200AC

CY7C1347C-200AC Summary of contents

Page 1

... Test Data-out (TDO). The JTAG circuitry is used to serially shift data to and from the device. JTAG inputs use LVTTL/LVCMOS levels to shift data during this testing mode of operation. The CY7C1347C/GVT71128DA36 GVT71256DA18 operate from a +3.3V power supply. All inputs and outputs are LVTTL compatible 7C1347C-250 ...

Page 2

... Power Down Logic OE# ADSP ADSC# ADV# A1-A0 MODE Note: 1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information. CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 [1] BYTE a WRITE D Q BYTE b WRITE D Q BYTE c WRITE D Q BYTE d WRITE ...

Page 3

... DQc 8 DQc CCQ DQc 12 DQc CY7C1347C GVT71128DA36 DQd 18 DQd CCQ DQd 22 DQd 23 DQd 24 DQd CCQ DQd 28 DQd 29 DQd 30 CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 100-Pin TQFP Top View NC 1 DQb DQb NC 3 DQb CCQ CCQ DQb DQb DQb 8 DQb 73 DQb 9 72 DQb CCQ 70 CCQ DQb ...

Page 4

... CCQ K DQd L DQd M V CCQ N DQd P DQd CCQ CCQ DQb CCQ DQb J V CCQ DQb M V CCQ N DQb CCQ CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 119-Ball BGA Top View CY7C1347C/GVT71128DA36 ADSP A CE2 A ADSC DQc DQc DQc DQc BWc ADV BWb DQc DQd V CLK DQd BWd NC ...

Page 5

... DQb. Data I/O are high impedance if either of these inputs are LOW, conditioned by BWE being LOW. BWE Input- Write Enable: This active LOW input gates byte write opera- Synchronous tions and must meet the setup and hold times around the rising edge of CLK. 5 CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 Description Description ...

Page 6

... Interleaved Burst. Burst Address Table (MODE = GND First Fourth Address Address (external) (internal) A...A00 A...A11 A...A01 A...A10 A...A10 A...A01 A...A11 A...A00 6 CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 Description Second Third Fourth Address Address Address (internal) (internal) (internal) A...A01 A...A10 A...A11 A...A10 A...A11 A...A00 A...A11 A...A00 A ...

Page 7

... ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification. 9. For X18 product, there are only BWa and BWb. CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 CE CE2 CE2 ADSP ...

Page 8

... Diagram). Output changes in response to the falling edge of TCK. This is the output side of the serial registers placed be- tween TDI and TDO. TDO is connected to the least significant bit (LSB) of any register. (See Figure 2.) CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 Performing a TAP Reset The TAP circuitry does not have a reset pin (TRST, which is optional in the IEEE 1149 ...

Page 9

... High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the ID register when the controller is in Cap- CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 ture-DR mode and places the ID register between the TDI and TDO pins in Shift-DR mode. The IDCODE instruction is the ...

Page 10

... TEST-LOGIC 1 RESET 0 1 REUN-TEST/ 0 IDLE Note: 10. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT- EXIT1- PAUSE- EXIT2-DR 1 UPDATE- Figure 1. TAP Controller State Diagram 10 1 SELECT IR-SCAN 0 1 CAPTURE-IR 0 SHIFT-IR ...

Page 11

... OLC [12, 14 100 A OHC [12 8.0 mA OLT [12 8.0 mA OHT (AC)<–0.5V for t<t /2, Power-up KHKH . Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 Selection Circuitry [11] Min. Max. 2 0.3 CC –0.3 0.8 –5.0 5.0 –30 30 –5.0 5 ...

Page 12

... Capture Hold CH Notes: 15. t and t refer to the set-up and hold time requirements of latching data from the boundary scan register 16. Test conditions are specified using the load in TAP AC Test Conditions. CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 [15, 16] Over the Operating Range Description 12 Min. Max Unit 20 ns ...

Page 13

... TAP Timing and Test Conditions TDO 1.5V (a) 9 CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 3. 1 ALL INPUT PULSES 1.5V 1 ...

Page 14

... Do not use these instructions; they are reserved for future use. 110 Do not use these instructions; they are reserved for future use. 111 Places the bypass register between TDI and TDO. This instruction does not affect device operations. 14 CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 Description Description ...

Page 15

... DQb 74 23 DQb 75 24 DQb 78 25 DQb 79 26 DQb ADV 83 30 ADSP 84 31 ADSC BWE CLK 89 CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 Boundary Scan Order (128K x 36) Bit# Signal Name Bump BWa 3T 38 BWb 4T 39 BWc 5T 40 BWd DQc 6M 46 DQc 7L 47 DQc 6K 48 ...

Page 16

... ADSP 84 23 ADSC BWE CLK 89 28 CE2 92 29 BWa 93 30 BWb 94 31 CE2 Note: 17 the case temperature. A CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 Boundary Scan Order (256K x 18) Signal Bit# Name Bump DQb 3T 36 DQb 5T 37 DQb 6R 38 DQb DQb 7P 41 DQb 6N 42 DQb 6L 43 ...

Page 17

... Max.; CLK frequency = 0 CC Device deselected; all inputs < > Max CLK cycle time > t min. KC Description Test Conditions MHz 3.3V CC Test Conditions 4-layer PCB 17 CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 Min. Max. 2.0 V +0.3 CC 2.0 4.6 –0.5 0.8 –5 5 –30 30 < V –5 5 OUT CC 2.4 0.4 3.135 3 ...

Page 18

... KQHZ KQLZ OEHZ 18 CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 ALL INPUT PULSES 90% 90% 10% 10% 1 200 MHz 166 MHz Max. Min. Max. Min. Max. 5.0 6.0 2.0 2 ...

Page 19

... CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active. 28. For X18 product, there are only BWa and BWb for byte write control OEQ OELZ Q(A1) Q(A2) Q(A2+1) 19 CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 Q(A2+2) Q(A2+3) Q(A2) Q(A2+1) BURST READ ...

Page 20

... Switching Waveforms (continued) [27, 28] Write Timing CLK t S ADSP# ADSC ADDRESS t H BWa#, BWb#, BWc#, BWd#, BWE#, GW# GW# CE# ADV# OE# t KQX DQ Q SINGLE WRITE CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 OEHZ D(A1) D(A2) D(A2+1) D(A2+1) D(A2+2) BURST WRITE 20 A3 D(A2+3) D(A3) D(A3+1) D(A3+2) BURST WRITE ...

Page 21

... Switching Waveforms (continued) [27, 28] Read/Write Timing CLK t S ADSP# ADSC ADDRESS A2 t BWa#, BWb#, BWc#, BWd#, BWE#, GW# CE# ADV# OE Q(A1) Q(A2) D(A3) Single Reads Single Write 21 CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 A5 Q(A4) Q(A4+1) Q(A4+2) D(A5) D(A5+1) Burst Read Burst Write ...

Page 22

... Ordering Information Speed (MHz) Ordering Code 250 CY7C1347C-250AC/ GVT71128DA36T-4 CY7C1347C-250BGC/ GVT71128DA36B-4 225 CY7C1347C-225AC/ GVT71128DA36T-4.4 CY7C1347C-225BGC/ GVT71128DA36B-4.4 200 CY7C1347C-200AC/ GVT71128DA36T-5 CY7C1347C-200BGC/ GVT71128DA36B-5 166 CY7C1347C-166AC/ GVT71128DA36T-6 CY7C1347C-16BGC/ GVT71128DA36B-6 250 CY7C1327C-250AC/ GVT71256DA18T-4 CY7C1327C-250BGC/ GVT71256DA18B-4 225 CY7C1327C-225AC/ GVT71256DA18T-4.4 CY7C1327C-225BGC/ GVT71256DA18B-4.4 200 CY7C1327C-200AC/ GVT71256DA18T-5 CY7C1327C-200BGC/ GVT71256DA18B-5 ...

Page 23

... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 23 51-85050-A ...

Page 24

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 119-Lead FBGA ( 2.4 mm) BG119 CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 51-85115 ...

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