CY7C1347C-200AC Cypress Semiconductor Corp, CY7C1347C-200AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1347C-200AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1347C-200AC

• Density: 4.5Mb
• Access Time (max): 2.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 200MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 4
• Supply Current: 360mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 128K
• Lead Free Status / Rohs Status: Not Compliant

128K X 36 Pin Descriptions
256K X 18 Pin Descriptions
5C, 6C, 2R, 6R,
5C, 6C, 2R, 6R,
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
1B, 7B, 1C, 7C,
1R, 5R, 7R, 1T,
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
X36 BGA Pins
X18 BGA Pins
4D, 3J, 5J, 4L,
2T, 3T, 5T, 6T
2T, 6T, 6U
3T, 4T, 5T
4M
4M
4N
5G
3G
4H
2U
3U
4U
5U
4N
3G
4P
5L
3L
4K
4E
6B
4P
5L
100, 99, 82, 81,
100, 99, 82, 81,
X36 QFP Pins
35, 34, 33, 32,
44, 45, 46, 47,
X18 QFP Pins
35, 34, 33, 32,
80, 48, 47, 46,
45, 44, 49, 50
48, 49, 50
14, 16, 66
37
36
93
94
95
96
87
88
89
98
92
38
39
43
42
37
36
93
94
87
Name
Name
BWE
BWE
BWa
BWb
BWc
BWd
TMS
TDO
BWa
BWb
CLK
CE2
TCK
GW
TDI
CE
NC
A0
A1
A0
A1
A
A
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Output
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Type
Type
Input
-
5
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
Byte Write: A byte write is LOW for a Write cycle and HIGH for
a Read cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high impedance
if either of these inputs are LOW, conditioned by BWE being
LOW.
Write Enable: This active LOW input gates byte write opera-
tions and must meet the set-up and hold times around the
rising edge of CLK.
Global Write: This active LOW input allows a full 36-bit Write
to occur independent of the BWE and BWn lines and must
meet the set-up and hold times around the rising edge of CLK.
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All
synchronous inputs must meet set-up and hold times around
the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP .
Chip Enable: This active LOW input is used to enable the
device.
IEEE 1149.1 test inputs. LVTTL-level inputs.
IEEE 1149.1 test output. LVTTL-level output.
No Connect: These signals are not internally connected.
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
Byte Write Enables: A byte write enable is LOW for a Write
cycle and HIGH for a Read cycle. BWa controls DQa. BWb
controls DQb. Data I/O are high impedance if either of these
inputs are LOW, conditioned by BWE being LOW.
Write Enable: This active LOW input gates byte write opera-
tions and must meet the setup and hold times around the rising
edge of CLK.
CY7C1347C/GVT71128DA36
CY7C1327C/GVT71256DA18
Description
Description