CY7C1361B-100AJC Cypress Semiconductor Corp, CY7C1361B-100AJC Datasheet - Page 12

• Manufacturer Part Number: CY7C1361B-100AJC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361B-100AJC

• Density: 9Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 180mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05302 Rev. *B
CY7C1363B: Pin Definitions
V
V
TDO
TDI
TMS
TCK
NC
V
SS
SSQ
SS
Name
/DNU
55,60,71,76,
1,2,3,6,7,16,
25,28,29,30,
38,39,42,51,
52,53,56,57,
66,75,78,79,
17,40,67,90 17,40,67,90 D3,D5,E3,
5,10,21,26,
Enable)
(3-Chip
TQFP
95,96
14
–
–
–
–
55,60,71,76,
1,2,3,6,7,16,
25,28,29,30,
38,39,42,43,
51,52,53,56,
57,66,75,78,
5,10,21,26,
79,95,96
Enable)
(2-Chip
TQFP
14
–
–
–
–
(continued)
C7,D2,D4,
,L7,P1,P6,
R1,R5,R7,
H5,K3,K5,
B1,B7,C1,
D7,E1,E6,
H2,F2,G1,
E5,F3,F5,
G6,H7,J3,
M6,N2,N7
N5,P3,P5
J5,K1,K6,
L4,L2,L7,
T1,T4,U6
Enable)
(2-Chip
G5,H3,
M5,N3,
L3,M3,
BGA
U5
U3
U2
U4
–
–
D10,E1,E10,
L11,M2,M11,
N7,N10,N11,
H7,J5,J6,J7,
K5,K6,K7,L5
G10,H3,H9,
H10,J2,J11,
C2,C10,D1,
B4,B11,C1,
F1,F10,G1,
M6,M7,N4,
K2,K11,L2,
C4,C5,C6,
C7,C8,D5,
G6,G7,H1,
H2,H5,H6,
,L6,L7,M5,
N2,N5,N6,
D6,D7,E5,
E6,E7,F5,
F6,F7,G5,
A1,A5,B1,
P1,P2,R2
Enable)
(3-Chip
fBGA
N8
R5
R7
P7
P5
–
–
Synchronous
Synchronous
Synchronous
Ground/DNU
JTAG serial
JTAG serial
JTAG serial
I/O Ground
Ground
output
JTAG-
Clock
input
input
I/O
–
Ground for the core of the device.
Ground for the I/O circuitry.
Serial data-out to the JTAG circuit.
Delivers data on the negative edge of TCK.
If the JTAG feature is not being utilized, this
pin should be left unconnected. This pin is
not available on TQFP packages.
Serial data-In to the JTAG circuit.
Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin
can be left floating or connected to V
through a pull up resistor. This pin is not
available on TQFP packages.
Serial data-In to the JTAG circuit.
Sampled on the rising edge of TCK. If the
JTAG feature is not being utilized, this pin
can be disconnected or connected to V
This pin is not available on TQFP packages.
Clock input to the JTAG circuitry. If the
JTAG feature is not being utilized, this pin
must be connected to V
available on TQFP packages.
No Connects. Not internally connected to
the die. 18M, 36M, 72M, 144M and 288M
are address expansion pins are not inter-
nally connected to the die.
This pin can be connected to Ground or
should be left floating.
Description
CY7C1361B
CY7C1363B
SS
. This pin is not
Page 12 of 34
DD
DD
.
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