CY7C1361B-100AJC Cypress Semiconductor Corp, CY7C1361B-100AJC Datasheet - Page 9

• Manufacturer Part Number: CY7C1361B-100AJC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361B-100AJC

• Density: 9Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 180mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05302 Rev. *B
CY7C1361B–Pin Definitions
CY7C1363B: Pin Definitions
V
V
TDO
TDI
TMS
TCK
NC
V
A
SS
SSQ
SS
0
, A
Name
Name
/DNU
1
, A
37,36,32,33,
34,35,43,44,
45,46,47,48,
49,50,80,81,
16,38,39,42,
17,40,67,90 17,40,67,90 H2,D3,E3,
55,60,71,76
5,10,21,26,
82,99,100
Enable)
(3-Chip
Enable)
(3-Chip
TQFP
TQFP
66
14
–
–
–
–
37,36,32,33,
34,35,44,45,
46,47,48,49,
50,80,81,82,
16,38,39,42,
55,60,71,76
5,10,21,26,
92,99,100
Enable)
(2-Chip
Enable)
(2-Chip
TQFP
TQFP
43,66
14
–
–
–
–
(continued)
P4,N4,A2,
C2,R2,T2,
A3,B3,C3,
B6,C6,R6,
T3,A5,B5,
C5,T5,A6,
P3,D5,E5,
B1,C1,R1,
R5,T6,U6,
F3,H3,K3,
F5,H5,K5,
M5,N5,P5
D4,L4,J5,
B7,C7,R7
T1,T2,J3,
Enable)
(2-Chip
Enable)
(2-Chip
M3,N3,
BGA
BGA
T6
U5
U3
U2
U4
–
-
A10,A11,B2,
J6,J7,K5,K6,
K7,L5,L6,L7,
B11,C2,C10,
P11,R3,R4,
R8,R9,R10,
H10,N2,N5,
N6,N7,N10,
B10,P3,P4,
P8,P9,P10,
M5,M6,M7,
A1,A11,B1,
G6,G7,H5,
R6,P6,A2,
C4,C5,C6,
C7,C8,D5,
H1,H3,H9,
D6,D7,E5,
F6,F7,G5,
E6,E7,F5,
H6,H7,J5,
P1,P2,R2
Enable)
(3-Chip
Enable)
(3-Chip
N4,N8
fBGA
fBGA
R11
P7
P5
R5
R7
–
-
Synchronous
Synchronous
Synchronous
Ground/DNU This pin can be connected to Ground or
Synchronous
JTAG serial
JTAG serial
JTAG serial
I/O Ground
Ground
output
JTAG-
Clock
Input-
input
input
I/O
I/O
–
Ground for the core of the device.
Ground for the I/O circuitry.
Serial data-out to the JTAG circuit.
Delivers data on the negative edge of TCK.
If the JTAG feature is not being utilized, this
pin should be left unconnected. This pin is
not available on TQFP packages.
Serial data-In to the JTAG circuit. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be left
floating or connected to V
up resistor. This pin is not available on TQFP
packages.
Serial data-In to the JTAG circuit. Sampled
on the rising edge of TCK. If the JTAG feature
is not being utilized, this pin can be discon-
nected or connected to V
available on TQFP packages.
Clock input to the JTAG circuitry. If the
JTAG feature is not being utilized, this pin
must be connected to V
available on TQFP packages.
No Connects. Not internally connected to
the die. 18M, 36M, 72M, 144M and 288M are
address expansion pins are not internally
connected to the die.
should be left floating.
Address Inputs used to select one of the
512K address locations. Sampled at the
rising edge of the CLK if ADSP or ADSC is
active LOW, and CE
sampled active. A
Description
Description
[1:0]
1
, CE
feed the 2-bit counter.
SS
CY7C1361B
CY7C1363B
DD
DD
. This pin is not
2
, and CE
. This pin is not
through a pull
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