CY7C1361B-100AJC Cypress Semiconductor Corp, CY7C1361B-100AJC Datasheet - Page 25

• Manufacturer Part Number: CY7C1361B-100AJC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1361B-100AJC

• Density: 9Mb
• Access Time (max): 8.5ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Number Of Ports: 1
• Supply Current: 180mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-05302 Rev. *B
Switching Characteristics
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes:
15. This part has a voltage regulator internally; t
16. t
17. At any given voltage and temperature, t
18. This parameter is sampled and not 100% tested.
19. Timing reference level is 1.5V when V
20. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
POWER
CYC
CH
CL
CDV
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
WEH
ADVH
DH
CEH
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions
CHZ
, t
CLZ
,t
OELZ
, and t
V
Clock Cycle Time
Clock HIGH
Clock LOW
Data Output Valid After CLK Rise
Data Output Hold After CLK Rise
Clock to Low-Z
Clock to High-Z
OE LOW to Output Valid
OE LOW to Output Low-Z
OE HIGH to Output High-Z
Address Set-up Before CLK Rise
ADSP, ADSC Set-up Before CLK Rise
ADV Set-up Before CLK Rise
GW, BWE, BW
Rise
Data Input Set-up Before CLK Rise
Chip Enable Set-up
Address Hold After CLK Rise
ADSP, ADSC Hold After CLK Rise
GW , BWE , BW
ADV Hold After CLK Rise
Data Input Hold After CLK Rise
Chip Enable Hold After CLK Rise
OEHZ
DD
(Typical) to the first Access
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
DDQ
Description
[A:D]
[16, 17, 18]
[A:D]
OEHZ
Over the Operating Range
[16, 17, 18]
= 3.3V and is 1.25V when V
POWER
Hold After CLK Rise
is less than t
Set-up Before CLK
is the time that the power needs to be supplied above V
[16, 17, 18]
[16, 17, 18]
OELZ
[15]
and t
CHZ
DDQ
is less than t
[19, 20]
= 2.5V.
Min.
7.5
3.0
3.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
0
0
0
133 MHz
CLZ
Max.
6.5
3.5
3.5
3.5
to eliminate bus contention between SRAMs when sharing the same
Min.
8.5
3.2
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
3.2
0.5
1
0
0
0
117 MHz
DD
(minimum) initially, before a read or write operation
Max.
7.5
3.5
3.5
3.5
Min.
4.0
4.0
2.0
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
10
1
0
0
0
100 MHz
CY7C1361B
CY7C1363B
Max.
8.5
3.5
3.5
3.5
Page 25 of 34
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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