CY7C1362A-200AC Cypress Semiconductor Corp, CY7C1362A-200AC Datasheet

CY7C1362A-200AC

Manufacturer Part Number

CY7C1362A-200AC

Description

Manufacturer

Cypress Semiconductor Corp

Datasheets

1.CY7C1362A-200AC.pdf (28 pages)

2.CY7C1362A-200AC.pdf (27 pages)

3.CY7C1362A-200AC.pdf (27 pages)

Specifications of CY7C1362A-200AC

Density

9Mb

Access Time (max)

3ns

Operating Supply Voltage (typ)

3.3V

Package Type

TQFP

Operating Temp Range

0C to 70C

Supply Current

510mA

Operating Supply Voltage (min)

3.14V

Operating Supply Voltage (max)

3.63V

Operating Temperature Classification

Commercial

Mounting

Surface Mount

Pin Count

100

Word Size

18b

Lead Free Status / Rohs Status

Not Compliant

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Features

Functional Description

The Cypress Synchronous Burst SRAM family employs

high-speed, low-power CMOS designs using advanced tri-

ple-layer polysilicon, double-layer metal technology. Each

memory cell consists of four transistors and two high-valued

resistors.

The

GVT71512D18 SRAMs integrate 262,144x36 and 524,288x18

SRAM cells with advanced synchronous peripheral circuitry

Selection Guide

Cypress Semiconductor Corporation

Maximum Access Time (ns)

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Fast clock speed: 225, 200, 166, and 150 MHz

• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns

• Optimal for depth expansion (one cycle chip deselect

• 3.3V –5% and +10% power supply

• 3.3V or 2.5V I/O supply

• 5V tolerant inputs except I/Os

• Clamp diodes to V

• Common data inputs and data outputs

• Byte Write Enable and Global Write control

• Multiple chip enables for depth expansion:

• Address pipeline capability

• Address, data, and control registers

• Internally self-timed Write Cycle

• Burst control pins (interleaved or linear burst se-

• Automatic power-down for portable applications

• JTAG boundary scan for B and T package version

• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid

to eliminate bus contention)

three chip enables for TA package version and two chip

enables for B and T package versions

quence)

Array) and 100-pin TQFP packages

CY7C1360A/GVT71256D36

at all inputs and outputs

and

Commercial

•

3901 North First Street

CY7C1362A/

256K x 36/512K x 18 Pipelined SRAM

PRELIMINARY

71256D36-4.4

71512D18-4.4

7C1360A-225

7C1362A-225

570

2.5

and a 2-bit counter for internal burst operation. All synchro-

nous inputs are gated by registers controlled by a posi-

tive-edge-triggered Clock Input (CLK). The synchronous in-

puts include all addresses, all data inputs, address-pipelining

Chip Enable (CE), depth-expansion Chip Enables (CE

ables (BWa, BWb, BWc, BWd, and BWE), and global write

(GW). However, the CE

the TA package version.

Asynchronous inputs include the Output Enable (OE) and

burst mode control (MODE). The data outputs (Q), enabled by

OE, are also asynchronous.

Addresses and chip enables are registered with either Ad-

dress Status Processor (ADSP) or Address Status Controller

(ADSC) input pins. Subsequent burst addresses can be inter-

nally generated as controlled by the Burst Advance Pin (ADV).

Address, data inputs, and write controls are registered on-chip

to initiate self-timed WRITE cycle. WRITE cycles can be one

to four bytes wide as controlled by the write control inputs.

Individual byte write allows individual byte to be written. BWa

controls DQa. BWb controls DQb. BWc controls DQc. BWd

controls DQd. BWa, BWb, BWc, and BWd can be active only

with BWE being LOW. GW being LOW causes all bytes to be

written. The x18 version only has 18 data inputs/outputs (DQa

and DQb) along with BWa and BWb (no BWc, BWd, DQc, and

DQd).

For the B and T package versions, four pins are used to imple-

ment JTAG test capabilities: Test Mode Select (TMS), Test Da-

ta-In (TDI), Test Clock (TCK), and Test Data-Out (TDO). The

JTAG circuitry is used to serially shift data to and from the

device. JTAG inputs use LVTTL/LVCMOS levels to shift data

during this testing mode of operation. The TA package version

does not offer the JTAG capability.

The

GVT71512D18 operate from a +3.3V power supply. All inputs

and outputs are LVTTL compatible.

), burst control inputs (ADSC, ADSP , and ADV), Write En-

CY7C1360A/GVT71256D36

•

7C1360A-200

7C1362A-200

71256D36-5

71512D18-5

San Jose

510

3.0

CY7C1360A/GVT71256D36

CY7C1362A/GVT71512D18

chip enable input is only available for

•

7C1360A-166

7C1362A-166

71256D36-6

71512D18-6

CA 95134

425

3.5

and

•

71256D36-6.7

71512D18-6.7

7C1360A-150

7C1362A-150

408-943-2600

CY7C1362A/

May 9, 2001

380

3.5

and

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