CY7C1362A-200AC Cypress Semiconductor Corp, CY7C1362A-200AC Datasheet - Page 5

• Manufacturer Part Number: CY7C1362A-200AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1362A-200AC

• Density: 9Mb
• Access Time (max): 3ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 510mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Lead Free Status / Rohs Status: Not Compliant

256K X 36 Pin Descriptions
6C, 2R, 6R, 3T, 4T, 5T
5B, 6B, 2C, 3C, 5C,
2A, 3A, 5A, 6A, 3B,
- (not available for
X36 PBGA Pins
PBGA)
5G
3G
4M
4G
4P
4N
4H
4K
4E
2B
4A
4B
3R
5L
3L
4F
7T
44, 45, 46, 47, 48,
92 (for TA Version
100, 99, 82, 81,
43 (TA Version)
X36 QFP Pins
35, 34, 33, 32,
92 (T Version)
49, 50
only)
37
36
93
94
95
96
87
88
89
98
97
86
83
84
85
31
64
PRELIMINARY
MODE
ADSP
ADSC
Name
BWE
BWa
BWb
BWc
BWd
CLK
ADV
CE
CE
GW
CE
OE
A0
A1
ZZ
A
2
2
Asynchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Input-
Static
Input-
Type
Input
5
Addresses: These inputs are registered and must meet
the set-up and hold times around the rising edge of CLK.
The burst counter generates internal addresses associ-
ated with A0 and A1, during burst cycle and wait cycle.
Byte Write: A byte write is LOW for a WRITE cycle and
HIGH for a READ cycle. BWa controls DQa. BWb con-
trols DQb. BWc controls DQc. BWd controls DQd. Data
I/O are high impedance if either of these inputs are LOW,
conditioned by BWE being LOW.
Write Enable: This active LOW input gates byte write
operations and must meet the set-up and hold times
around the rising edge of CLK.
Global Write: This active LOW input allows a full 36-bit
WRITE to occur independent of the BWE and BWn lines
and must meet the set-up and hold times around the
rising edge of CLK.
Clock: This signal registers the addresses, data, chip
enables, write control, and burst control inputs on its ris-
ing edge. All synchronous inputs must meet set-up and
hold times around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP .
Chip Enable: This active HIGH input is used to enable
the device.
Chip Enable: This active LOW input is used to enable the
device. Not available for B and T package versions.
Output Enable: This active LOW asynchronous input en-
ables the data output drivers.
Address Advance: This active LOW input is used to con-
trol the internal burst counter. A HIGH on this pin gener-
ates wait cycle (no address advance).
Address Status Processor: This active LOW input, along
with CE being LOW, causes a new external address to
be registered and a READ cycle is initiated using the new
address.
Address Status Controller: This active LOW input caus-
es the device to be deselected or selected along with
new external address to be registered. A READ or
WRITE cycle is initiated depending upon write control
inputs.
Mode: This input selects the burst sequence. A LOW on
this pin selects Linear Burst. A NC or HIGH on this pin
selects Interleaved Burst.
Snooze: This active HIGH input puts the device in low
power consumption standby mode. For normal opera-
tion, this input has to be either LOW or NC (No Connect).
CY7C1360A/GVT71256D36
CY7C1362A/GVT71512D18
Description