CY7C1362A-200AC Cypress Semiconductor Corp, CY7C1362A-200AC Datasheet - Page 6

• Manufacturer Part Number: CY7C1362A-200AC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1362A-200AC

• Density: 9Mb
• Access Time (max): 3ns
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temp Range: 0C to 70C
• Supply Current: 510mA
• Operating Supply Voltage (min): 3.14V
• Operating Supply Voltage (max): 3.63V
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Word Size: 18b
• Lead Free Status / Rohs Status: Not Compliant

256K X 36 Pin Descriptions
512K X 18 Pin Descriptions
(c) 2D, 1D, 1E, 2E, 2F,
3D, 5D, 3E, 5E, 3F, 5F,
1A, 7A, 1F, 7F, 1J, 7J,
3H, 5H, 3K, 5K, 3M,
2A, 3A, 5A, 6A, 3B,
5B, 6B, 2C, 3C, 5C,
(b) 7H, 6H, 7G, 6G,
6C, 2R, 6R, 2T, 3T,
6M, 6L, 7L, 6K, 7K,
1B, 7B, 1C, 7C, 4D,
2M, 1N, 2N, 1P , 2P
5M, 3N, 5N, 3P , 5P
6F, 6E, 7E, 7D, 6D,
(d) 1K, 2K, 1L, 2L,
3J, 5J, 4L, 1R, 5R,
(a) 6P , 7P , 7N, 6N,
4C, 2J, 4J, 6J, 4R
7R, 1T, 2T, 6T, 6U
X18 PBGA Pins
X36 PBGA Pins
1G, 2G, 1H, 2H,
1M, 7M, 1U, 7U
5T, 6T
4N
3G
4M
4H
4P
4K
4E
5L
2U
3U
4U
5U
80, 48, 47, 46, 45,
for B and T version
for B and T version
40, 55, 60, 67, 71,
(a) 51, 52, 53, 56,
(b) 68, 69, 72, 73,
(c) 1, 2, 3, 6, 7, 8,
(d) 18, 19, 22, 23,
57, 58, 59, 62, 63
74, 75, 78, 79, 80
24, 25, 28, 29, 30
100, 99, 82, 81,
5, 10, 17, 21, 26,
4, 11, 20, 27, 54,
43 (TA Version)
38, 39, 42 for TA
X18 QFP Pins
35, 34, 33, 32,
92 (T Version)
X36 QFP Pins
15, 41, 65, 91
44, 49, 50
61, 70, 77
14, 16, 66
9, 12, 13
Version
76, 90
37
36
93
94
87
88
89
98
38
39
43
42
(continued)
PRELIMINARY
Name
BWE
BWa
BWb
CLK
Name
GW
V
CE
DQa
DQb
DQd
TMS
TDO
DQc
TCK
A0
A1
V
V
TDI
NC
A
CCQ
CC
SS
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
Synchronous
I/O Supply
Ground
Input-
Input-
Input-
Input-
Input-
Input-
Output
Output
Supply
Type
Input/
Type
Input
-
6
Addresses: These inputs are registered and must meet
the set up and hold times around the rising edge of CLK.
The burst counter generates internal addresses associ-
ated with A0 and A1, during burst cycle and wait cycle.
Byte Write Enables: A byte write enable is LOW for a
WRITE cycle and HIGH for a READ cycle. BWa controls
DQa. BWb controls DQb. Data I/O are high impedance if
either of these inputs are LOW, conditioned by BWE be-
ing LOW.
Write Enable: This active LOW input gates byte write op-
erations and must meet the set-up and hold times around
the rising edge of CLK.
Global Write: This active LOW input allows a full 18-bit
WRITE to occur independent of the BWE and WEn lines
and must meet the set-up and hold times around the ris-
ing edge of CLK.
Clock: This signal registers the addresses, data, chip en-
ables, write control and burst control inputs on its rising
edge. All synchronous inputs must meet set-up and hold
times around the clock’s rising edge.
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP .
Data Inputs/Outputs: First Byte is DQa. Second Byte is
DQb. Third Byte is DQc. Fourth Byte is DQd. Input data
must meet set-up and hold times around the rising edge
of CLK.
IEEE 1149.1 test inputs. LVTTL-level inputs. Not avail-
able for TA package version.
IEEE 1149.1 test output. LVTTL-level output. Not avail-
able for TA package version.
Core power Supply: +3.3V –5% and +10%
Ground: GND.
Output Buffer Supply: +2.5V or +3.3V.
No Connect: These signals are not internally connected.
User can leave it floating or connect it to V
CY7C1360A/GVT71256D36
CY7C1362A/GVT71512D18
Description
Description
CC
or V
SS
.