CY7C63413-PVXC Cypress Semiconductor Corp, CY7C63413-PVXC Datasheet - Page 11

• Manufacturer Part Number: CY7C63413-PVXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63413-PVXC

• Cpu Family: enCoRe II
• Device Core: M8C
• Device Core Size: 8b
• Frequency (max): 12MHz
• Interface Type: USB
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 24
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25/5.5V
• Operating Supply Voltage (min): 4/4.35V
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: SSOP
• Lead Free Status / Rohs Status: Compliant

Document #: 38-08027 Rev. *B
initialization noted under “Reset,” bit 6 of the Processor Status
and Control Register is set to “1” to indicate to the firmware
that a Watch Dog Reset occurred.
The Watch Dog Timer is a 2-bit timer clocked by a 4.096-ms
clock (bit 11) from the free-running timer. Writing any value to
the write-only Watch Dog Clear I/O port (0x26) will clear the
Watch Dog Timer.
In some applications, the Watch Dog Timer may be cleared in
the 1.024-ms timer interrupt service routine. If the 1.024-ms
timer interrupt service routine does not get executed for 8.192
ms or more, a Watch Dog Timer Reset will occur. A Watch Dog
Timer Reset lasts for 2.048 ms after which the microcontroller
begins execution at ROM address 0x0000. The USB trans-
mitter is disabled by a Watch Dog Reset because the USB
Device Address Register is cleared. Otherwise, the USB
Controller would respond to all address 0 transactions. The
USB transmitter remains disabled until the MSB of the USB
address register is set.
.
Table 2. Port 0 Data
Table 3. Port 1 Data
Table 4. Port 2 Data
P0[7]
P1[7]
P2[7]
R/W
R/W
R/W
Addr: 0x00
Addr: 0x01
Addr: 0x02
P0[6]
P1[6]
P2[6]
R/W
R/W
R/W
Internal
Data Bus
GPIO
CFG
Interrupt
Enable
P0[5]
P1[5]
P2[5]
R/W
R/W
R/W
Internal
Buffer
Figure 4. Block Diagram of a GPIO Line
Port Write
Port Read
Data
Out
Latch
P0[4]
P1[4]
P2[4]
R/W
R/W
R/W
Port 0 Data
Port 1 Data
Port 2 Data
mode
2 bits
General Purpose I/O Ports
Ports 0 to 2 provide 24 GPIO pins that can be read or written.
Each port (8 bits) can be configured as inputs with internal pull-
ups, open drain outputs, or traditional CMOS outputs. Please
note an open drain output is also a high-impedance (no pull-
up) input. All of the I/O pins within a given port have the same
configuration. Ports 0 to 2 are considered low current drive
with typical current sink capability of 7 mA.
The internal pull-up resistors are typically 7 kΩ. Two factors
govern the enabling and disabling of the internal pull-up
resistors: the port configuration selected in the GPIO Configu-
ration register and the state of the output data bit. If the GPIO
Configuration selected is “Resistive” and the output data bit is
“1,” then the internal pull-up resistor is enabled for that GPIO
pin. Otherwise, Q1 is turned off and the 7-kΩ pull-up is
disabled. Q2 is “ON” to sink current whenever the output data
bit is written as a “0.” Q3 provides “HIGH” source current when
the GPIO port is configured for CMOS outputs and the output
data bit is written as a “1”. Q2 and Q3 are sized to sink and
source, respectively, roughly the same amount of current to
support traditional CMOS outputs with symmetric drive.
P0[3]
P1[3]
P2[3]
R/W
R/W
R/W
Q2
Q1
7 kΩ
to Interrupt
Controller
V
CC
Q3
ESD
P0[2]
P1[2]
P2[2]
R/W
R/W
R/W
GPIO
Pin
P0[1]
P1[1]
P2[1]
R/W
R/W
R/W
CY7C63413C
CY7C63513C
CY7C63613C
Page 11 of 32
P0[0]
P1[0]
P2[0]
R/W
R/W
R/W
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