CY7C63413-PVXC Cypress Semiconductor Corp, CY7C63413-PVXC Datasheet - Page 20

• Manufacturer Part Number: CY7C63413-PVXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63413-PVXC

• Cpu Family: enCoRe II
• Device Core: M8C
• Device Core Size: 8b
• Frequency (max): 12MHz
• Interface Type: USB
• Program Memory Type: EPROM
• Program Memory Size: 8KB
• Total Internal Ram Size: 256Byte
• # I/os (max): 24
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.25/5.5V
• Operating Supply Voltage (min): 4/4.35V
• Instruction Set Architecture: RISC
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: SSOP
• Lead Free Status / Rohs Status: Compliant

Document #: 38-08027 Rev. *B
Interrupt Vectors
The Interrupt Vectors supported by the USB Controller are
listed in Table 27. Although Reset is not an interrupt, per se,
the first instruction executed after a reset is at PROM address
Table 27.Interrupt Vector Assignments
Interrupt Latency
Interrupt latency can be calculated from the following
equation:
Interrupt Latency =(Number of clock cycles remaining in the
For example, if a 5 clock cycle instruction such as JC is being
executed when an interrupt occurs, the first instruction of the
Interrupt Service Routine will execute a min. of 16 clocks
(1+10+5) or a max. of 20 clocks (5+10+5) after the interrupt is
issued. Remember that the interrupt latches are sampled at
the rising edge of the last clock cycle in the current instruction.
USB Bus Reset Interrupt
The USB Bus Reset interrupt is asserted when a USB bus
reset condition is detected. A USB bus reset is indicated by a
single ended zero (SE0) on the upstream port for more than 8
microseconds.
Timer Interrupt
There are two timer interrupts: the 128-µs interrupt and the
1.024-ms interrupt. The user should disable both timer inter-
rupts before going into the suspend mode to avoid possible
conflicts between servicing the interrupts first or the suspend
request first.
USB Endpoint Interrupts
There are three USB endpoint interrupts, one per endpoint.
The USB endpoints interrupt after the either the USB host or
the USB controller sends a packet to the USB.
Interrupt Vector Number
not applicable
current instruction)
+ (10 clock cycles for the CALL instruction)
+ (5 clock cycles for the JMP instruction)
10
12
11
1
2
3
4
5
6
7
8
9
ROM Address
0x000A
0x000C
0x000E
0x0000
0x0002
0x0004
0x0006
0x0008
0x0010
0x0012
0x0014
0x0016
0x0018
0x0000—which corresponds to the first entry in the Interrupt
Vector Table. Because the JMP instruction is 2 bytes long, the
interrupt vectors occupy 2 bytes.
DAC Interrupt
Each DAC I/O pin can generate an interrupt, if enabled.The
interrupt polarity for each DAC I/O pin is programmable. A
positive polarity is a rising edge input while a negative polarity
is a falling edge input. All of the DAC pins share a single
interrupt vector, which means the firmware will need to read
the DAC port to determine which pin or pins caused an
interrupt.
Please note that if one DAC pin triggered an interrupt, no other
DAC pins can cause a DAC interrupt until that pin has returned
to its inactive (non-trigger) state or the corresponding interrupt
enable bit is cleared. The USB Controller does not assign
interrupt priority to different DAC pins and the DAC Interrupt
Enable Register is not cleared during the interrupt
acknowledge process.
GPIO Interrupt
Each of the 32 GPIO pins can generate an interrupt, if enabled.
The interrupt polarity can be programmed for each GPIO port
as part of the GPIO configuration. All of the GPIO pins share
a single interrupt vector, which means the firmware will need
to read the GPIO ports with enabled interrupts to determine
which pin or pins caused an interrupt.
Please note that if one port pin triggered an interrupt, no other
port pins can cause a GPIO interrupt until that port pin has
returned to its inactive (non-trigger) state or its corresponding
port interrupt enable bit is cleared. The USB Controller does
not assign interrupt priority to different port pins and the Port
Interrupt Enable Registers are not cleared during the interrupt
acknowledge process.
Execution after Reset begins here
USB Bus Reset interrupt
128-µs timer interrupt
1.024-ms timer interrupt
USB Address A Endpoint 0 interrupt
USB Address A Endpoint 1 interrupt
USB Address A Endpoint 2 interrupt
Reserved
Reserved
Reserved
DAC interrupt
GPIO interrupt
Reserved
Function
CY7C63413C
CY7C63513C
CY7C63613C
Page 20 of 32
[+] Feedback