CY7C65640-LFC Cypress Semiconductor Corp, CY7C65640-LFC Datasheet - Page 6

• Manufacturer Part Number: CY7C65640-LFC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65640-LFC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 70C
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

2.0
Cypress’s TetraHub is a high-performance self-powered Universal Serial Bus (USB) 2.0 hub. The Tetra architecture provides
four downstream USB ports, with a Transaction Translator (TT) for each port, making it the highest-performance hub possible.
This single-chip device incorporates one upstream and four downstream USB transceivers, a Serial Interface Engine (SIE), USB
Hub Controller and Repeater, and four TTs. It is suitable for standalone hubs, motherboard hubs, and monitor hub applications.
Being a fixed-function USB device, there is no risk or added engineering effort required for firmware development. The developer
does not need to write any firmware for their design. The CY4602 Tetrahub USB 2.0 4-port Hub Reference Design Kit provides
all materials and documents needed to move rapidly into production. The reference design kit includes board schematics, bill of
materials, Gerber files, Orcad files, key application notes, and product description.
2.1
Figure 2-1 is a block diagram of the TetraHub Architecture.
2.2
The SIE allows the CY7C65640 to communicate with the USB host through the USB repeater component of the hub. The SIE
handles the following USB bus activity independently of the Hub Control Block:
Document #: 38-08019 Rev. *E
• Bit stuffing/unstuffing
• Checksum generation/checking
• ACK/NAK/STALL
• TOKEN type identification
• Address checking.
Crystal
24 MHz
D+ D–
TetraHub Architecture
USB Serial Interface Engine (SIE)
USB 2.0
Introduction
USB Downstream Port 1
PHY
PWR#[1]
D+
USB Upstream Port
Port Power
PLL
Hub Repeater
Control
USB 2.0 PHY
OVR#[1] LED
Status
Port
D–
D+
USB 2.0
PHY
USB Downstream Port 2
D–
PWR#[2]
Port Power
Control
Figure 2-1. Block Diagram
OVR#[2] LED
Interface
Engine
Serial
Routing Logic
Status
Port
D+
USB 2.0
Transaction Translator (X4)
USB Downstream Port 3
PHY
D–
PWR#[3]
TT RAM
Port Power
Control
OVR#[3] LED
Status
Port
D+ D–
USB Control Logic
USB 2.0
SPI Communication
USB Downstream Port 4
PHY
High-Speed
Block
PWR#[4]
Port Power
Control
OVR#[4] LED
CY7C65640
Status
Port
Page 6 of 27
SPI_SCK
SPI_SD
SPI_CS