PI7C8154BNA Pericom Semiconductor, PI7C8154BNA Datasheet - Page 29

• Manufacturer Part Number: PI7C8154BNA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNA

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

06-0008
2.7.3
2.7.4
If extra read transactions could have side effects, for example, when accessing a FIFO, use non-
prefetchable read transactions to those locations. Accordingly, if it is important to retain the value
of the byte enable bits during the data phase, use non-prefetchable read transactions. If these
locations are mapped in memory space, use the memory read command and map the target into
non-prefetchable (memory-mapped I/O) memory space to use non-prefetching behavior.
READ PREFETCH ADDRESS BOUNDARIES
PI7C8154B imposes internal read address boundaries on read prefetched data. When a read
transaction reaches one of these aligned address boundaries, the PI7C8154B stops pre-fetched data,
unless the target signals a target disconnect before the read prefetched boundary is reached. When
PI7C8154B finishes transferring this read data to the initiator, it returns a target disconnect with the
last data transfer, unless the initiator completes the transaction before all pre-fetched read data is
delivered. Any leftover pre-fetched data is discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned 4KB address
boundary, or until the initiator de-asserts FRAME#. Section 2.7.6 describes flow-through mode
during read operations.
Table 2-4 shows the read pre-fetch address boundaries for read transactions during non-flow-
through mode.
Table 2-4 READ PREFETCH ADDRESS BOUNDARIES
- does not matter if it is prefetchable or non-prefetchable
* don’t care
Table 2-5 READ TRANSACTION PREFETCHING
See Section 3.3 for detailed information about prefetchable and non-prefetchable address spaces.
DELAYED READ REQUESTS
PI7C8154B treats all read transactions as delayed read transactions, which means that the read
request from the initiator is posted into a delayed transaction queue. Read data from the target is
Type of Transaction
Configuration Read
I/O Read
Memory Read
Memory Read
Memory Read
Memory Read Line
Memory Read Line
Memory Read Multiple
Memory Read Multiple
Type of Transaction
I/O Read
Configuration Read
Memory Read
Memory Read Line
Memory Read Multiple
Address Space
-
-
Non-Prefetchable
Prefetchable
Prefetchable
-
-
-
-
Read Behavior
Prefetching never allowed
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Upstream: Prefetching used or programmable
Prefetching always used
Prefetching always used
Page 29 of 111
Cache Line Size
(CLS)
CLS = 0 or 16
*
*
*
CLS = 0 or 16
CLS = 1, 2, 4, 8
CLS = 0 or 16
CLS = 1, 2, 4, 8
CLS = 1, 2, 4, 8
Prefetch Aligned Address Boundary
One DWORD (no prefetch)
One DWORD (no prefetch)
One DWORD (no prefetch)
16-DWORD aligned address boundary
Cache line address boundary
16-DWORD aligned address boundary
Cache line boundary
Queue full
Second cache line boundary
MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B