PI7C8154BNA Pericom Semiconductor, PI7C8154BNA Datasheet - Page 56

• Manufacturer Part Number: PI7C8154BNA
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8154BNA

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

06-0008
5.2.4
Similarly, for upstream delayed write transactions, when the parity error is detected on the initiator
bus and PI7C8154B has write status to return, the following events occur:
For downstream transactions, where the parity error is being passed back from the target bus and
the parity error condition was not originally detected on the initiator bus, the following events
occur:
For upstream transactions, when the parity error is being passed back from the target bus and the
parity error condition was not originally detected on the initiator bus, the following events occur:
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when the bridge responds as a target, it detects a data
parity error on the initiator (primary) bus and the following events occur:
Similarly, during upstream posted write transactions, when the bridge responds as a target, it
detects a data parity error on the initiator (secondary) bus, the following events occur:
PI7C8154B first asserts S_TRDY# and then asserts S_PERR# two cycles later; if the
secondary interface parity-error-response bit is set in the bridge control register (offset 3Ch).
PI7C8154B sets the secondary interface parity-error-detected bit in the secondary status
register.
Because there was not an exact data and parity match, the write status is not returned and the
transaction remains in the queue.
Bridge asserts P_PERR# two cycles after the data transfer, if the following are both true:
Bridge completes the transaction normally.
Bridge asserts S_PERR# two cycles after the data transfer, if the following are both true:
Bridge completes the transaction normally.
Bridge asserts P_PERR# two cycles after the data transfer, if the parity error response bit is set
in the command register of primary interface.
Bridge sets the parity error detected bit in the status register of the primary interface.
Bridge captures and forwards the bad parity condition to the secondary bus.
Bridge completes the transaction normally.
Bridge asserts S_PERR# two cycles after the data transfer, if the parity error response bit is set
in the bridge control register of the secondary interface.
Bridge sets the parity error detected bit in the status register of the secondary interface.
Bridge captures and forwards the bad parity condition to the primary bus.
Bridge completes the transaction normally.
The parity-error-response bit is set in the command register of the primary interface
The parity-error-response bit is set in the bridge control register of the secondary interface
The parity error response bit is set in the command register of the primary interface.
The parity error response bit is set in the bridge control register of the secondary interface.
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MARCH 2006 REVISION 1.12
ASYNCHRONOUS 2-PORT
PCI-to-PCI BRIDGE
PI7C8154B