JS28F256P30T95 Micron Technology Inc, JS28F256P30T95 Datasheet - Page 23

• Manufacturer Part Number: JS28F256P30T95
• Manufacturer: Micron Technology Inc

Specifications of JS28F256P30T95

• Cell Type: NOR
• Density: 256Mb
• Access Time (max): 95/17ns
• Interface Type: Parallel/Serial
• Boot Type: Top
• Address Bus: 24b
• Operating Supply Voltage (typ): 1.8V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Program/erase Volt (typ): 1.7 to 2/8.5 to 9.5V
• Sync/async: Async/Sync
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 1.7V
• Operating Supply Voltage (max): 2V
• Word Size: 16b
• Number Of Words: 16M
• Supply Current: 28mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Compliant

P30
5.4
5.5
Note:
August 2008
Order Number: 306666-12
memory contents at the aborted location (for a program) or block (for an erase) are no longer
valid, because the data may have been only partially written or erased.
If RST# is asserted during a program or erase operation, the operation is terminated and the
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, I
measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby,
average current is measured over the same time interval 5 μs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase
operation, it continues to consume active power until the program or erase operation is
completed.
Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
flash memory if it is the system boot device. If a CPU reset occurs with no flash
memory reset, improper CPU initialization may occur because the flash memory may
be providing status information rather than array data. Flash memory devices from
Numonyx allow proper CPU initialization following a system reset through the use of the
RST# input. RST# should be controlled by the same low-true reset signal that resets
the system CPU.
After initial power-up or reset, the device defaults to asynchronous Read Array mode,
and the Status Register is set to 0x80. Asserting RST# de-energizes all internal
circuits, and places the output drivers in High-Z. When RST# is asserted, the device
shuts down the operation in progress, a process which takes a minimum amount of
time to complete. When RST# has been deasserted, the device is reset to
asynchronous Read Array state.
When returning from a reset (RST# deasserted), a minimum wait is required before the
initial read access outputs valid data. Also, a minimum delay is required after a reset
before a write cycle can be initiated. After this wake-up interval passes, normal
operation is restored. See
about signal-timing.
Section 15.0, “AC Characteristics” on page 55
CCS
, is the average current
for details
Datasheet
23