PI7C8150BND Pericom Semiconductor, PI7C8150BND Datasheet - Page 56

• Manufacturer Part Number: PI7C8150BND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

Table 6-4. Setting Secondary Interface Master Data Parity Error Detected Bit
Table 6-5. Assertion of P_PERR#
Table 6–4 shows setting the data parity detected bit in the status register of secondary
interface. This bit is set under the following conditions:
!
!
!
Table 6–5 shows assertion of P_PERR_L. This signal is set under the following conditions:
!
!
!
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
Secondary
Detected
Detected Bit
0
1
0
0
0
1
0
0
0
1
0
0
X= don’t care
P_PERR#
1 (de-asserted)
1
0 (asserted)
1
0
1
1
1
0
0
1
1
X = don’t care
2
The PI7C8150 must be a master on the secondary bus.
The parity error response bit must be set in the bridge control register of secondary
interface.
The S_PERR_L signal is detected asserted or a parity error is detected on the
secondary bus.
PI7C8150 is either the target of a write transaction or the initiator of a read transaction
on the primary bus.
The parity-error-response bit must be set in the command register of primary interface.
PI7C8150 detects a data parity error on the primary bus or detects S_PERR_L asserted
during the completion phase of a downstream delayed write transaction on the target
(secondary) bus.
Parity
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
Transaction Type
Read
Read
Read
Read
Posted Write
Posted Write
Posted Write
Posted Write
Delayed Write
Delayed Write
Delayed Write
Delayed Write
46
Direction
Downstream
Upstream
Direction
Downstream
Downstream
Upstream
Upstream
Downstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
Downstream
Downstream
Upstream
Upstream
March 19, 2003 – Revision 1.04
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Primary
Secondary
Bus Where Error
Bus Where Error
2-PORT PCI-TO-PCI BRIDGE
Was Detected
Was Detected
ADVANCE INFORMATION
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / 1
x / x
x / x
x / x
x / x
1 / x
x / x
1 / x
x / x
x / x
x / x
1 / x
1 / 1
x / x
x / x
Secondary Parity
Secondary Parity
Error Response
Error Response
Primary /
Primary/
Bits
Bits
PI7C8150