PI7C8150BND Pericom Semiconductor, PI7C8150BND Datasheet - Page 72

• Manufacturer Part Number: PI7C8150BND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

14
14.1
CONFIGURATION REGISTERS
PCI configuration defines a 64-byte space (configuration header) to define various
attributes of PI7C8150 as shown below.
CONFIGURATION REGISTER
1011
1100
1101
1110
1111
Bus Arbiter
Preemption
Secondary
Control
Secondary Latency
Reserved
Timer
31-24
Upstream (S to P) Memory Limit
Prefetchable Memory Limit
Upstream Memory Control
I/O Limit Upper 16-bit
Secondary Status
Arbiter Control
Primary Status
Memory Limit
Bridge Control
Device ID
Configuration Write
Memory Read
Multiple
Dual Address Cycle
Memory Read Line
Memory Write and
Invalidate
Upstream (S to P) Memory Base Upper 32-bit
Subordinate Bus
Header Type
Class Code
Reserved
Number
23-16
Prefetchable Limit Upper 32-bit
Prefetchable Base Upper 32-bit
62
Hot Swap Switch Time Slot
Reserved
Reserved
Reserved
Reserved
I. Type 0 Configuration Write: Ignore
II. Type 1 Configuration Write (not special cycle
request):Ignore
III. Configuration Write as Special Cycle Request (device
= 1Fh, function = 7h):
1. If the target bus is the bridge’s primary bus: claim and
pass through as a Special Cycle
2. If the target bus is neither the primary bus nor is it in range
of buses defined by the bridge’s secondary and subordinate
bus registers: claim and pass through unchanged as a Type 1
Configuration Write.
3. If the target bus is not the bridge’s primary bus, but is in
range of buses defined by the bridge’s secondary and
subordinate bus registers: ignore.
Same as Memory Read
Supported
Same as Memory Read
Same as Memory Read
Primary Latency Timer
Secondary Bus
I/O Limit
Reserved
Number
Upstream (S to P) Memory Base
15-8
Prefetchable Memory Base
Diagnostic / Chip Control
March 19, 2003 – Revision 1.04
Extended Chip Control
I/O Base Upper 16-bit
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Memory Base
Vendor ID
Command
Primary Bus Number
Capability Pointer to
Cache Line Size
Interrupt Line
Revision ID
I/O Base
DCh
7-0
PI7C8150
Address
4Ch
0Ch
1Ch
2Ch
3Ch
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
44h
48h
50h
54h