PI7C8150BND Pericom Semiconductor, PI7C8150BND Datasheet - Page 79

• Manufacturer Part Number: PI7C8150BND
• Manufacturer: Pericom Semiconductor

Specifications of PI7C8150BND

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Package Type: BGA
• Rad Hardened: No
• Lead Free Status / Rohs Status: Not Compliant

14.1.20
14.1.21
14.1.22
14.1.23
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h
PREFETCHABLE MEMORY BASE ADDRESS UPPER 32-BITS
REGISTER – OFFSET 28h
PREFETCHABLE MEMORY LIMIT ADDRESS UPPER 32-BITS
REGISTER – OFFSET 2Ch
I/O BASE ADDRESS UPPER 16-BITS REGISTER – OFFSET 30h
3:0
15:4
Bit
19:16
31:20
Bit
31:0
Bit
31:0
Bit
64-bit addressing
Prefetchable
Memory Base
Address [31:20]
Function
64-bit addressing
Prefetchable
Memory Limit
Address [31:20]
Function
Prefetchable
Memory Base
Address, Upper
32-bits [63:32]
Function
Prefetchable
Memory Limit
Address, Upper
32-bits [63:32]
Function
R/O
R/W
Type
R/O
R/W
Type
R/W
Type
R/W
Type
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
Defines the bottom address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be 0.
Description
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
Defines the top address of an address range for the bridge to
determine when to forward memory read and write transactions from
one interface to the other. The upper 12 bits correspond to address
bits [31:20] and are writable. The lower 20 bits are assumed to be
FFFFFh.
Description
Defines the upper 32-bits of a 64-bit bottom address of an address
range for the bridge to determine when to forward memory read and
write transactions from one interface to the other.
Reset to 0
Description
Defines the upper 32-bits of a 64-bit top address of an address range
for the bridge to determine when to forward memory read and write
transactions from one interface to the other.
Reset to 0
Description
69
March 19, 2003 – Revision 1.04
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
PI7C8150