PALCE16V8Z-25PI Lattice, PALCE16V8Z-25PI Datasheet - Page 31

• Manufacturer Part Number: PALCE16V8Z-25PI
• Description: SPLD PAL® Family 8 Macro Cells 50MHz EECMOS Technology 5V 20-Pin PDIP
• Manufacturer: Lattice

Specifications of PALCE16V8Z-25PI

• Package: 20PDIP
• Family Name: PAL®
• Maximum Propagation Delay Time: 25 ns
• Typical Operating Supply Voltage: 5 V
• Maximum Internal Frequency: 50 MHz
• Number Of Product Terms Per Macro: 8
• Re-programmability Support: Yes

CONNECTION DIAGRAMS
Top View
PIN DESIGNATIONS
CLK
GND = Ground
I
I/O
OE
V
Note:
Pin 1 is marked for orientation.
CC
= Clock
= Input
= Input/Output
= Output Enable
= Supply Voltage
CLK/I
GND
I
I
I
I
I
I
I
I
0
1
2
3
4
5
6
7
8
DIP/SOIC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PALCE16V8 and PALCE16V8Z Families
V
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OE/I
CC
7
6
5
4
3
2
1
0
9
16493E-9
I
I
I
I
I
3
4
5
6
7
4
5
6
7
8
3
9
10 11 12 13
2
PLCC
1
20 19
18
17
16
15
14
I/O
I/O
I/O
I/O
I/O
16493E-10
6
5
4
3
2
31