MACH215-15JC Lattice, MACH215-15JC Datasheet - Page 17

• Manufacturer Part Number: MACH215-15JC
• Description: CPLD MACH 2 Family 64 Macro Cells 45.5MHz EECMOS Technology 5V 44-Pin PLCC
• Manufacturer: Lattice

Specifications of MACH215-15JC

• Package: 44PLCC
• Family Name: MACH 2
• Number Of Macro Cells: 64
• Maximum Propagation Delay Time: 15 ns
• Number Of User I/os: 32
• Number Of Logic Blocks/elements: 4
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 45.5 MHz
• Number Of Product Terms Per Macro: 12
• Memory Type: EEPROM
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

SWITCHING CHARACTERISTICS over INDUSTRIAL operating ranges (Note 2)
(continued)
Notes:
1. These parameters are not 100% tested, but are evaluated at initial characterization and at any time the design is modified
2. See Switching Test Circuit for test conditions. Switching waveforms illustrate true clocks only. Switching waveforms can be
3. Parameters measured with 16 outputs switching.
Parameter
Symbol
fMAXIR
tWICL
tWICH
tWIGL
tPDLL
tIGOL
tSLLA
tIGSA
tSLLS
tIGSS
tARW
tAPW
tARR
tPDL
tAPR
where frequency may be affected.
used to illustrate both synchronous and asynchronous clock timing. For example, t SS is the t S parameter for synchronous
clocks and t SA is the t S parameter for asynchronous clocks.
tHIR
tICO
tIGO
tSIR
tICS
tSIL
tHIL
tAR
tAP
tEA
tER
Parameter Description
Input, I/O, or Feedback to Output Through
Transparent Input or Output Latch
Input Register Setup Time
Input Register Hold Time
Input Register Clock to Combinatorial Output
Input Register Clock to Output Register Setup
Maximum Input Register Frequency
Input Latch Setup Time
Input Latch Hold Time
Input Latch Gate to Combinatorial Output
Input Latch Gate to Output Through Transparent
Output Latch
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Product Term Output
Latch Gate
Input Latch Gate to Output Latch Setup Using
Product Term Output Latch Gate
Setup Time from Input, I/O, or Feedback Through
Transparent Input Latch to Global Output Latch Gate
Input Latch Gate to Output Latch Setup Using Global
Output Latch Gate
Input Latch Gate Width LOW
Input, I/O, or Feedback to Output Through Transparent
Input and Output Latches
Asynchronous Reset to Registered or Latched Output
Asynchronous Reset Width (Note 1)
Asynchronous Reset Recovery Time (Note 1)
Asynchronous Preset to Registered or Latched Output
Asynchronous Preset Width (Note 1)
Asynchronous Preset Recovery Time (Note 1)
Input, I/O, or Feedback to Output Enable (Note 3)
Input, I/O, or Feedback to Output Disable (Note 3)
Input Register Clock Width
MACH215-14/18/24 (Ind)
1/(tWICL + tWICH )
D-type
T-type
LOW
HIGH
66.5
14.5
14.5
14.5
Min
2.4
7.5
7.5
2.5
8.5
8.5
7.5
16
11
16
10
10
3
3
-14
Max
20.5
19.5
19.5
19.5
14.5
14.5
17
18
23
66.5
19.5
14.5
19.5
Min
2.4
3.5
7.5
7.5
2.5
3.5
7.5
18
10
10
18
12
18
12
-18
Max
20.5
26.5
22
24
23
24
24
18
18
25.5
25.5
Min
2.4
2.5
24
10
10
50
12
12
18
10
24
18
24
18
4
4
-24
Max
26.5
32.5
28
30
29
30
30
24
24
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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