MT4LC16M4H9DJ-5 Micron Technology Inc, MT4LC16M4H9DJ-5 Datasheet - Page 9

• Manufacturer Part Number: MT4LC16M4H9DJ-5
• Description: DRAM Chip EDO 64M-Bit 16Mx4 3.3V 32-Pin SOJ Tray
• Manufacturer: Micron Technology Inc
• Type: EDOr

Specifications of MT4LC16M4H9DJ-5

• Package: 32SOJ
• Density: 64 Mb
• Address Bus Width: 12 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Random Access Time: 50 ns
• Operating Temperature: 0 to 70 °C

NOTES
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. V
9. In addition to meeting the transition rate
10. If CAS# and RAS# = V
11. If CAS# = V
12. Measured with a load equivalent to two TTL
13. If CAS# is LOW at the falling edge of RAS#,
14. The
15. The
16. Either
16 Meg x 4 EDO DRAM
D22_2.p65 – Rev. 5/00
MHz; T
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
indicate cycle time at which proper operation
over the full temperature range is ensured.
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the
refresh requirement is exceeded.
measuring timing of input signals. Transition
times are measured between V
between V
specification, all input signals must transit
between V
monotonic manner.
the last valid READ cycle.
gates and 100pF; and V
output data will be maintained from the previous
cycle. To initiate a new cycle and clear the data-
out buffer, CAS# must be pulsed HIGH for
t
only. If
(MAX) limit, then access time was controlled
exclusively by
applied). With or without the
t
t
only. If
(MAX) limit, then access time was controlled
exclusively by
applied). With or without the
and
cycle.
RAD (MAX) was specified as a reference point
AA,
RCD (MAX) was specified as a reference point
CC
IH
is dependent on output loading and cycle
(MIN) and V
t
t
t
t
RAD (MAX) limit is no longer specified.
RCD (MAX) limit is no longer specified.
CAC must always be met.
RAC, and
t
RCH or
A
t
t
RAD was greater than the specified
RCD was greater than the specified
= 25°C.
IL
IH
IL
and V
and V
, data output may contain data from
t
t
t
AA (
CAC (
t
RRH must be satisfied for a READ
CAC must always be met.
IL
(MAX) are reference levels for
IH
IL
t
).
RAC and
(or between V
t
IH
RAC [MIN] no longer
, data output is High-Z.
OL
= 0.8V and V
t
T = 2.5ns.
SS
CC
.
t
IH
CAC no longer
t
t
RAD (MAX) limit,
RCD limit,
= +3.3V; f = 1
and V
IL
and V
IL
OH
(or
= 2V.
t
t
IH
t
AA
REF
CP.
t
t
) in a
RAD
RCD
9
17.
18.
19. These parameters are referenced to CAS# leading
20. If OE# is tied permanently LOW, LATE WRITE or
21. A HIDDEN REFRESH may also be performed after
22. RAS#-ONLY REFRESH requires that all rows be
23. The DQs open during READ cycles once
24. LATE WRITE and READ-MODIFY-WRITE cycles
25. Column address changed once each cycle.
26. V
27. NC pins are assumed to be left floating and are
t
achieves the open circuit condition and is not
referenced to V
t
operating parameters.
WRITE cycles. If
an EARLY WRITE cycle and the data output will
remain an open circuit throughout the entire
cycle.
MODIFY-WRITE cycles. Meeting these limits
allows for reading and disabling output data and
then applying input data. OE# held HIGH and
WE# taken LOW after CAS# goes LOW results in a
LATE WRITE (OE#-controlled) cycle.
t
LATE WRITE cycle.
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
READ-MODIFY-WRITE operations are not
possible.
a WRITE cycle. In this case, WE# is LOW and
OE# is HIGH.
refreshed at least once every 64ms (4,096 rows
for the H9 version and 8,192 rows for the G3
version). CBR REFRESH requires that at least
4,096 cycles be completed every 64ms.
t
brought HIGH, the DQs will open. If OE# is
brought back LOW (CAS# still LOW), the DQs
will provide the previously read data.
must have both
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. If OE# is taken back LOW while CAS#
remains LOW, the DQs will remain open.
width ≤ 10ns, and the pulse width cannot be
greater than one third of the cycle rate. V
undershoot: V
10ns, and the pulse width cannot be greater than
one third of the cycle rate.
not tested for leakage.
OFF (MAX) defines the time at which the output
WCS,
RWD,
OFF occur. If CAS# stays LOW while OE# is
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IH
overshoot: V
t
t
RWD,
RWD,
t
CWD, and
t
t
AWD, and
AWD, and
IL
OH
t
IH
(MIN) = -2V for a pulse width ≤
t
OD and
WCS >
or V
(MAX) = V
t
AWD are not applicable in a
t
OL
WCS applies to EARLY
.
t
t
t
CWD are not restrictive
WCS (MIN), the cycle is
t
OEH met (OE# HIGH
CWD define READ-
CC
16 MEG x 4
EDO DRAM
+ 2V for a pulse
©2000, Micron Technology, Inc.
OBSOLETE
t
WCS,
t
OD or
IL