CY37128P100-100AC Cypress Semiconductor Corp, CY37128P100-100AC Datasheet - Page 3

• Manufacturer Part Number: CY37128P100-100AC
• Description: CPLD Ultra37000 Family 3.8K Gates 128 Macro Cells 100MHz CMOS Technology 5V 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY37128P100-100AC

• Package: 100TQFP
• Family Name: Ultra37000
• Device System Gates: 3800
• Number Of Macro Cells: 128
• Maximum Propagation Delay Time: 12 ns
• Number Of User I/os: 69
• Number Of Logic Blocks/elements: 8
• Typical Operating Supply Voltage: 5 V
• Maximum Operating Frequency: 100 MHz
• Number Of Product Terms Per Macro: 16
• Memory Type: EEPROM
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

Document #: 38-03007 Rev. *B
Speed Bins
Device-Package Offering & I/O Count
Architecture Overview of Ultra37000 Family
Programmable Interconnect Matrix
The Programmable Interconnect Matrix (PIM) consists of a
completely global routing matrix for signals from I/O pins and
feedbacks from the logic blocks. The PIM provides extremely
robust interconnection to avoid fitting and density limitations.
The inputs to the PIM consist of all I/O and dedicated input pins
and all macrocell feedbacks from within the logic blocks. The
number of PIM inputs increases with pin count and the number
of logic blocks. The outputs from the PIM are signals routed to
the appropriate logic blocks. Each logic block receives 36
inputs from the PIM and their complements, allowing for 32-bit
operations to be implemented in a single pass through the
device. The wide number of inputs to the logic block also
improves the routing capacity of the Ultra37000 family.
An important feature of the PIM is its simple timing. The propa-
gation delay through the PIM is accounted for in the timing
specifications for each device. There is no additional delay for
traveling through the PIM. In fact, all inputs travel through the
PIM. As a result, there are no route-dependent timing param-
eters on the Ultra37000 devices. The worst-case PIM delays
are incorporated in all appropriate Ultra37000 specifications.
Routing signals through the PIM is completely invisible to the
user. All routing is accomplished by software—no hand routing
is necessary. Warp™ and third-party development packages
automatically route designs for the Ultra37000 family in a
matter of minutes. Finally, the rich routing resources of the
Ultra37000 family accommodate last minute logic changes
while maintaining fixed pin assignments.
Shaded areas indicate preliminary speed bins.
CY37032V
CY37064V
CY37128V
CY37192V
CY37256V
CY37384V
CY37512V
CY37032V
CY37064V
CY37128V
CY37192V
CY37256V
CY37384V
CY37512V
Device
Device
37
37
200
37
37
37
167
37
37
69
69
154
69
69
69
143
X
X
X
X
69
85
Logic Block
The logic block is the basic building block of the Ultra37000
architecture. It consists of a product term array, an intelligent
product-term allocator, 16 macrocells, and a number of I/O
cells. The number of I/O cells varies depending on the device
used. Refer to Figure 1 for the block diagram.
Product Term Array
Each logic block features a 72 x 87 programmable product
term array. This array accepts 36 inputs from the PIM, which
originate from macrocell feedbacks and device pins. Active
LOW and active HIGH versions of each of these inputs are
generated to create the full 72-input field. The 87 product
terms in the array can be created from any of the 72 inputs.
Of the 87 product terms, 80 are for general-purpose use for
the 16 macrocells in the logic block. Four of the remaining
seven product terms in the logic block are output enable (OE)
product terms. Each of the OE product terms controls up to
eight of the 16 macrocells and is selectable on an individual
macrocell basis. In other words, each I/O cell can select
between one of two OE product terms to control the output
buffer. The first two of these four OE product terms are
available to the upper half of the I/O macrocells in a logic block.
The other two OE product terms are available to the lower half
of the I/O macrocells in a logic block.
The next two product terms in each logic block are dedicated
asynchronous set and asynchronous reset product terms. The
final product term is the product term clock. The set, reset, OE
and product term clock have polarity control to realize OR
functions in a single pass through the array.
133
125
133
125
X
X
133
Ultra37000 CPLD Family
165
165
165
100
X
X
X
X
165
197
197
197
83
X
X
X
197
Page 3 of 63
269
66
X
X
X
X
269