XC3190A-4PQ160C Xilinx Inc, XC3190A-4PQ160C Datasheet - Page 24
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XC3190A-4PQ160C
Manufacturer Part Number
XC3190A-4PQ160C
Description
FPGA XC3100A Family 6K Gates 320 Cells 227MHz CMOS Technology 5V 160-Pin PQFP
Manufacturer
Xilinx Inc
Datasheet
1.XC3190A-4PQ160C.pdf
(76 pages)
Specifications of XC3190A-4PQ160C
Package
160PQFP
Family Name
XC3100A
Device Logic Units
320
Device System Gates
6000
Number Of Registers
928
Maximum Internal Frequency
227 MHz
Typical Operating Supply Voltage
5 V
Maximum Number Of User I/os
138
Ram Bits
64160
Re-programmability Support
Yes
Case
QFP160
Dc
98+
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XC3000 Series Field Programmable Gate Arrays
Notes: 1. At power-up, V
Figure 24: Master Serial Mode Programming Switching Characteristics
7-26
CCLK
Serial Data In
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode devices is
3. Master-serial-mode timing is based on slave-mode testing.
Serial DOUT
holding RESET Low until V
non-monotonically rising V
after VCC has reached 4.0 V (2.5 V for the XC3000L).
High.
(Output)
(Output)
CCLK
Data In setup
Data In hold
Description
CC
n – 3
must rise from 2.0 V to V
1
CC
CC
T
DSCK
may require >6- s High level on RESET, followed by a >6- s Low level on RESET and D/P
n
has reached 4.0 V (2.5 V for the XC3000L). A very long V
1
2
T
C
DSCK
KDS
Symbol
CC
n – 2
min in less than 25 ms. If this is not possible, configuration can be delayed by
2 T
CKDS
n + 1
Min
n – 1
60
0
n + 2
CC
rise time of >100 ms, or a
November 9, 1998 (Version 3.1)
Max
n
Units
X3223
ns
ns
R