XC3190A-4PQ160C Xilinx Inc, XC3190A-4PQ160C Datasheet - Page 63
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XC3190A-4PQ160C
Manufacturer Part Number
XC3190A-4PQ160C
Description
FPGA XC3100A Family 6K Gates 320 Cells 227MHz CMOS Technology 5V 160-Pin PQFP
Manufacturer
Xilinx Inc
Datasheet
1.XC3190A-4PQ160C.pdf
(76 pages)
Specifications of XC3190A-4PQ160C
Package
160PQFP
Family Name
XC3100A
Device Logic Units
320
Device System Gates
6000
Number Of Registers
928
Maximum Internal Frequency
227 MHz
Typical Operating Supply Voltage
5 V
Maximum Number Of User I/os
138
Ram Bits
64160
Re-programmability Support
Yes
Case
QFP160
Dc
98+
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XC3000 Series Pin Assignments
Xilinx offers the six different array sizes in the XC3000 families in a variety of surface-mount and through-hole package
types, with pin counts from 44 to 208.
Each chip is offered in several package types to accommodate the available PC board space and manufacturing technology.
Most package types are also offered with different chips to accommodate design changes without the need for PC board
changes.
Note that there is no perfect match between the number of bonding pads on the chip and the number of pins on a package.
In some cases, the chip has more pads than there are pins on the package, as indicated by the information (“unused” pads)
below the line in the following table. The IOBs of the unconnected pads can still be used as storage elements if the specified
propagation delays and set-up times are acceptable.
In other cases, the chip has fewer pads than there are pins on the package; therefore, some package pins are not connected
(n.c.), as shown above the line in the following table.
XC3000 Series 44-Pin PLCC Pinouts
XC3000A, XC3000L, and XC3100A families have identical pinouts
Peripheral mode and Master Parallel mode are not supported in the PC44 package
November 9, 1998 (Version 3.1)
Pin No.
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
R
TCLKIN-I/O
M1-RDATA
M0-RTRIG
PWRDWN
XC3030A
HDC-I/O
LDC-I/O
INIT-I/O
M2-I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XC3000 Series Field Programmable Gate Arrays
Pin No.
41
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
42
43
44
XTL1(OUT)-BCLK-I/O
XTL2(IN)-I/O
DONE-PGM
DOUT-I/O
XC3030A
RESET
DIN-I/O
CCLK
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7-65
7