P87C554SBAA NXP Semiconductors, P87C554SBAA Datasheet - Page 11

• Manufacturer Part Number: P87C554SBAA
• Description: MCU 8-Bit 87C 80C51 CISC 16KB EPROM 5V 68-Pin PLCC Tube
• Manufacturer: NXP Semiconductors

Specifications of P87C554SBAA

• Package: 68PLCC
• Device Core: 80C51
• Family Name: 87C
• Maximum Speed: 16 MHz
• Ram Size: 512 Byte
• Program Memory Size: 16 KB
• Operating Supply Voltage: 5 V
• Data Bus Width: 8 Bit
• Program Memory Type: EPROM
• Number Of Programmable I/os: 40
• Interface Type: I2C/UART
• On-chip Adc: 7-chx10-bit
• Operating Temperature: 0 to 70 °C
• Number Of Timers: 3

4. The 256-bytes expanded RAM (ERAM, 00H – FFH) are indirectly
Philips Semiconductors
Expanded Data RAM Addressing
The 8xC554 has internal data memory that is mapped into four
separate segments: the lower 128 bytes of RAM, upper 128 bytes of
RAM, 128 bytes Special Function Register (SFR), and 256 bytes
expanded RAM (EXTRAM).
The four segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are
3. The Special Function Registers, SFRs, (addresses 80H to FFH)
The Lower 128 bytes can be accessed by either direct or indirect
addressing. The Upper 128 bytes can be accessed by indirect
addressing only. The Upper 128 bytes occupy the same address
space as the SFR. That means they have the same address, but are
physically separate from SFR space.
When an instruction accesses an internal location above address
7FH, the CPU knows whether the access is to the upper 128 bytes
of data RAM or to SFR space by the addressing mode used in the
instruction. Instructions that use direct addressing access SFR
space. For example:
accesses the SFR at location 0A0H (which is P2). Instructions that
use indirect addressing access the Upper 128 bytes of data RAM.
2003 Jan 28
80C51 8-bit microcontroller – 6-clock operation
16K/512 OTP/ROMless, 7 channel 10 bit A/D, I
high I/O, 64L LQFP
MOV 0A0H,#data
directly and indirectly addressable.
indirectly addressable only.
are directly addressable only.
accessed by move external instruction, MOVX, and with the
EXTRAM bit cleared, see Figure 4.
NOTE:
*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that
case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
AUXR
Symbol
AO
EXTRAM
LVADC
—
Address = 8EH
Not Bit Addressable
Bit:
Function
Disable/Enable ALE
AO
0
1
Internal/External RAM (00H – FFH) access using MOVX @Ri/@DPTR
EXTRAM
0
1
Enable A/D low voltage operation
LVADC
0
1
Not implemented, reserved for future use*.
—
7
Operating Mode
ALE is emitted at a constant rate of 1/6 the oscillator frequency.
ALE is active only during a MOVX or MOVC instruction.
Operating Mode
Internal ERAM (00H–FFH) access using MOVX @Ri/@DPTR
External data memory access.
Operating Mode
Turns off A/D charge pump.
Turns on A/D charge pump. Required for operation below 4V.
—
6
—
5
Figure 4. AUXR: Auxiliary Register
—
4
2
C, PWM, capture/compare,
11
—
3
generate either read or write signals on P3.6 (#WR) and P3.7 (#RD).
For example:
where R0 contains 0A0H, accesses the data byte at address 0A0H,
rather than P2 (whose address is 0A0H).
The ERAM can be accessed by indirect addressing, with EXTRAM
bit cleared and MOVX instructions. This part of memory is physically
located on-chip, logically occupies the first 256-bytes of external
data memory.
With EXTRAM = 0, the EXTRAM is indirectly addressed, using the
MOVX instruction in combination with any of the registers R0, R1 of
the selected bank or DPTR. An access to ERAM will not affect ports
P0, P3.6 (WR#) and P3.7 (RD#). P2 SFR is output during expanded
RAM addressing. For example, with EXTRAM = 0,
where R0 contains 0A0H, accesses the ERAM at address 0A0H
rather than external memory. An access to external data memory
locations higher than FFH (i.e., 0100H to FFFFH) will be performed
with the MOVX DPTR instructions in the same way as in the
standard 80C51, so with P0 and P2 as data/address bus, and P3.6
and P3.7 as write and read timing signals. Refer to Figure 5.
With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar
to the standard 80C51. MOVX @ Ri will provide an 8-bit address
multiplexed with data on Port 0 and any output port pins can be
used to output higher order address bits. This is to provide the
external paging capability. MOVX @DPTR will generate a 16-bit
address. Port 2 outputs the high-order eight address bits (the
contents of DPH) while Port 0 multiplexes the low-order eight
address bits (DPL) with data. MOVX @Ri and MOVX @DPTR will
The stack pointer (SP) may be located anywhere in the 256 bytes
RAM (lower and upper RAM) internal data memory. The stack may
not be located in the ERAM address space.
MOV @R0,#data
MOVX @R0,#data
LVADC
2
EXTRAM
1
AO
0
Reset Value = xxxx x110B
80C554/87C554
Product data
SU00979A