ADC1175-50CIMTX National Semiconductor, ADC1175-50CIMTX Datasheet - Page 17

• Manufacturer Part Number: ADC1175-50CIMTX
• Description: ADC Single Pipelined 50MSPS 8-Bit Parallel 24-Pin TSSOP T/R
• Manufacturer: National Semiconductor

Specifications of ADC1175-50CIMTX

• Package: 24TSSOP
• Resolution: 8 Bit
• Sampling Rate: 50000 KSPS
• Architecture: Pipelined
• Number Of Analog Inputs: 1
• Digital Interface Type: Parallel
• Input Type: Voltage
• Signal To Noise Ratio: 48(Typ) dB
• Polarity Of Input Voltage: Unipolar

device. The LMH6702 and the LMH6609 have been found to
be an excellent device for driving the ADC1175-50. Also re-
member to use the RC between the driving source and the
ADC input, as explained in Section 1.0.
Driving the V
not source or sink the current required by the ladder. As
mentioned in Section 2.0, care should be taken to see that
any driving devices can source sufficient current into the
V
pins are not driven with devices than can handle the required
current, these reference pins will not be stable, resulting in a
reduction of dynamic performance.
Using a clock source with excessive jitter, using exces-
sively long clock signal trace, or having other signals
coupled to the clock signal trace. This will cause the sam-
pling interval to vary, causing excessive output noise and a
reduction in SNR performance. Simple gates with RC timing
is generally inadequate as a clock source.
Input test signal contains harmonic distortion that inter-
feres with the measurement of dynamic signal to noise
ratio. Harmonic and other interfering signals can be removed
by inserting a filter at the signal input. Suitable filters are
FIGURE 7. A 5.5 MHz Low Pass filter to eliminate harmonics at the signal input. Use with maximum input frequencies of
FIGURE 8. An 11 MHz Low Pass filter to eliminate harmonics at the signal input. Use with maximum input frequencies of
RT
pin and sink sufficient current from the V
RT
pin or the V
RB
pin with devices that can
RB
pin. If these
5 MHz to 10 MHz
1 MHz to 5 MHz.
17
shown in Figure 7 and Figure 8. The circuit of Figure 7 has a
cutoff of about 5.5 MHz and is suitable for input frequencies
of 1 MHz to 5 MHz. The circuit of Figure 8 has a cutoff of about
11 MHz and is suitable for input frequencies of 5 MHz to 10
MHz. These filters should be driven by a generator of 75Ω
source impedance and terminated with a 75Ω resistor.
Not considering the effect on a driven CMOS digital cir-
cuit(s) when the ADC1175-50 is in the power down
mode. Because the ADC1175-50 output goes into a high
impedance state when in the power down mode, any CMOS
device connected to these outputs will have their inputs float-
ing when the ADC is in power down. Should the inputs of the
circuit being driven by the ADC digital outputs float to a level
near 2.5V, a CMOS device could exhibit relative large supply
currents as the input stage toggles rapidly. The solution is to
use pull-down resistors at the ADC outputs. The value of
these resistors is not critical, as long as they do not cause
excessive currents in the outputs of the ADC1175-50. Low
pull-down resistor values could result in degraded SNR and
SINAD performance of the ADC1175-50. Values between 5
kΩ and 10 kΩ should work well.
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