ADC1175-50CIMTX National Semiconductor, ADC1175-50CIMTX Datasheet - Page 4

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ADC1175-50CIMTX

Manufacturer Part Number
ADC1175-50CIMTX
Description
ADC Single Pipelined 50MSPS 8-Bit Parallel 24-Pin TSSOP T/R
Manufacturer
National Semiconductor
Datasheet

Specifications of ADC1175-50CIMTX

Package
24TSSOP
Resolution
8 Bit
Sampling Rate
50000 KSPS
Architecture
Pipelined
Number Of Analog Inputs
1
Digital Interface Type
Parallel
Input Type
Voltage
Signal To Noise Ratio
48(Typ) dB
Polarity Of Input Voltage
Unipolar

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3 thru 10
(1 thru 8)
(22, 24)
(13, 16)
(18, 19)
11, 13,
(9, 11,
15, 18
20, 21
2, 24
(10)
Pin
No.
12)
12
14
Symbol
D0–D7
DV
DV
AV
AV
CLK
DD
DD
SS
SS
Equivalent Circuit
4
CMOS/TTL compatible digital clock input. V
the falling edge of CLK input.
Conversion data digital Output pins. D0 is the LSB, D7 is
the MSB. Valid data is output just after the rising edge of
the CLK input. These pins are in a high impedance mode
when the PD pin is low.
Positive digital supply pin. Connect to a quiet voltage source
of +5V. AV
be separately bypassed with a 10 µF capacitor and a 0.1
µF ceramic chip capacitor. See Section 4.0 for more
information.
The ground return for the digital supply. AV
should be connected together close to the ADC1175-50.
Positive analog supply pin. Connect to a quiet voltage
source of +5V. AV
source and be separately bypassed with a 10 µF capacitor
and a 0.1 µF ceramic chip capacitor. See Section 4.0 for
more information.
The ground return for the analog supply. AV
should be connected together close to the ADC1175-50
package.
DD
and DV
DD
DD
and DV
Description
should have a common source and
DD
should have a common
IN
SS
SS
is sampled on
and DV
and DV
SS
SS

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