ISL5416KI Intersil, ISL5416KI Datasheet - Page 20

• Manufacturer Part Number: ISL5416KI
• Description: Up/Down Conv Mixer 1.8V 256-Pin BGA
• Manufacturer: Intersil

Specifications of ISL5416KI

• Package: 256BGA
• Operating Supply Voltage: 1.8 V

INTERPOLATE BY 2 AND RE-SAMPLER, INTERPOLATE BY 2
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-80
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-80
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10
10
10
0
0
0
0
FIGURE 7F. FIR2, IHBF AND RESAMPLER COMPOSITE
0
0
FIGURE 7E. FIR2 AND IHBF COMPOSITE RESPONSE
RESPONSES (FIR2 OUTPUT AT 7.68 MHz WITH IHBF,
FIGURE 7D. INDIVIDUAL AND COMPOSITE
0. 5
0.5
1
5
1
RESPONSE
20
1. 5
1.5
10
2
2
2.5
2. 5
x 10
x 10
x 10
15
3
3
6
7
7
ISL5416
Two NCOs and two counters set the sample rates through
the rate change section. NCO1 sets the output sample rate
of the resampling filter. NCO1 is 48 bits and is updated at the
clock rate, so its output frequency is:
where N1 is the 48-bit programming word. The carry output
of the phase accumulator is used as the output clock, so
there can be one clock period of jitter. NCO2 is programmed
for the input sample rate to the resampler (equals the half-
band filter output rate). NCO2 is updated at the NCO1 output
rate. NCO2 controls the phase of the resampling filter. This
NCO also has a 48-bit phase accumulator. The equation for
programming the output frequency of NCO2 is:
when the resampling filter is enabled and
when the resampling filter is bypassed. NCO2 can have one
output sample period (Fout
period when the HOIF is bypassed).
A static phase offset can be programmed for NCO2. The
range of the phase offset is 0 to 2 NCO2 output sample
periods (0 - 2 resampling filter input sample periods). The
programming resolution is 1/256 of a resampling filter input
sample period. This programmable offset allows the user
vary the group delay of one channel relative to another in
very fine increments to compensate for differences in system
delays.
If the resampler is not needed for rate change, it can be used
for phase shifting by setting bit 22 in IWA *001h.
While the 48-bit phase accumulators provide very good
frequency programming resolution, at some input/output
sample rate ratios, there will be a slow phase drift due to the
finite word length. To correct for this, a “leap” counter is
provided to reset the phase of the NCOs after a programmed
interval to remove any accumulated error. The leap counter
is 32 bits. If properly programmed, this phase correction will
not be seen in the output of the part.
The input rate to the IHBF/RS section must match the output
sample rate of FIR2, i.e. the output rate of NCO2 must equal
the input sample rate of the part divided by the decimation
factors in the CIC, FIR1, and FIR2. The leap counter can
guarantees this over the long term, but due to the jitter of the
phase accumulator outputs, a FIFO is provided to guarantee
that there are no dropped samples. The FIFO is filled at the
output sample rate of the AGC and is emptied by Fout
Fout
to a depth of two before the NCOs are enabled. This
minimum fill depth guarantees that there are enough
samples in the FIFO that the FIFO never empties or
overflows due to NCO jitter if the NCOs and leap counter are
properly programmed. FIFO reads are enabled after an
Fout
Fout
Fout
2
/2 if the IHBF is enabled). After reset, the FIFO is filled
2
2
1
= Fout
= Fclk * N
= Fclk * N
1
* N
2
1
2
/ 2
/ 2
/ 2
48
48
48
,
1
= Fclk * (N
period) of jitter (one clock
1
/ 2
48
) * (N
2
/ 2
48
2
(or
)