70V659S12BFI Integrated Device Technology (Idt), 70V659S12BFI Datasheet

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70V659S12BFI

Manufacturer Part Number
70V659S12BFI
Description
SRAM Chip Async Dual 3.3V 4.5M-Bit 128K x 36 12ns 208-Pin CABGA
Manufacturer
Integrated Device Technology (Idt)
Datasheet
1.IDT70V657S10DRG.pdf (24 pages)

Specifications of 70V659S12BFI

Package
208CABGA
Timing Type
Asynchronous
Density
4.5 Mb
Typical Operating Supply Voltage
3.3 V
Address Bus Width
17 Bit
Number Of I/o Lines
36 Bit
Number Of Ports
2
Number Of Words
128K
©2008 Integrated Device Technology, Inc.
Features
Functional Block Diagram
NOTES:
1. A
2. BUSY is an input as a Slave (M/S=V
3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed access
– Commercial: 10/12/15ns (max.)
– Industrial: 12/15ns (max.)
Dual chip enables allow for depth expansion without
external logic
IDT70V659/58/57 easily expands data bus width to 72 bits
or more using the Master/Slave select when cascading
more than one device
M/S = V
M/S = V
Busy and Interrupt Flags
On-chip port arbitration logic
16
is a NC for IDT70V658. Also, Addresses A
IL
IH
for BUSY input on Slave
for BUSY output flag on Master,
BE
BE
BE
BE
CE
R/ W
CE
OE
3L
2L
1L
0L
0L
1L
L
L
I/O
BUSY
0L-
A
SEM
16 L (1)
INT
I/O
A
L (2,3)
35L
0L
L
L (3)
IL
) and an output when it is a Master (M/S=V
CE
CE
16
Decoder
Address
0L
1L
and A
HIGH-SPEED 3.3V
128/64/32K x 36
ASYNCHRONOUS DUAL-PORT
STATIC RAM
15
TDO
R/W
TDI
are NC's for IDT70V657.
OE
L
L
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Di n_L
ADDR_L
128/64/32K x 36
ARBITRATION
SEMAPHORE
B
E
0
L
INTERRUPT
MEMORY
B
E
1
L
ARRAY
JTAG
LOGIC
B
E
2
L
M/S
B
E
3
L
1
B
E
3
R
Dout18-26_R
Dout27-35_R
Dout9-17_R
B
E
2
R
Dout0-8_R
ADDR_R
B
E
1
R
Di n_R
IH
B
E
0
R
).
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
Separate byte controls for multiplexed bus and bus
matching compatibility
Supports JTAG features compliant to IEEE 1149.1
LVTTL-compatible, single 3.3V (±150mV) power supply for
core
LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port
Available in a 208-pin Plastic Quad Flatpack, 208-ball fine
pitch Ball Grid Array, and 256-ball Ball Grid Array
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
R/W
OE
TMS
TCK
TRST
R
R
Address
Decoder
CE
CE
0R
1R
IDT70V659/58/57S
BUSY
SEM
INT
4869 drw 01
R (3)
R
R (2,3)
OE
R/ W
A
A
CE
CE
I/O
OCTOBER 2008
BE
BE
BE
BE
16R (1)
0R
R
0R -
0R
1R
R
3R
2R
1R
0R
I/O
35R
DSC-4869/7

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70V659S12BFI Summary of contents

Page 1

Features True Dual-Port memory cells which allow simultaneous access of the same memory location High-speed access – Commercial: 10/12/15ns (max.) – Industrial: 12/15ns (max.) Dual chip enables allow for depth expansion without external logic IDT70V659/58/57 easily expands data bus width ...

Page 2

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Description The IDT70V659/58/ high-speed 128/64/32K x 36 Asynchro- nous Dual-Port Static RAM. The IDT70V659/58/57 is designed to be used as a stand-alone 4/2/1Mbit Dual-Port RAM ...

Page 3

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Pin Configurations (3,4,5,6,7,8) 03/19/04 1 I/O 19L I/O 2 19R 3 I/O 20L 4 I/O 20R 5 V DDQL I/O 21L I/O 8 21R I/O 9 ...

Page 4

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Pin Configurations (3,4,5,6,7,8 03/19/ TDI I/O NC TDO NC 18L 16L (1) I/O I/O V ...

Page 5

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Pin Configuration (3,4,5,6,7,8) 03/19/ I/O I/O V 19L TDO 18L SS B I/O V I/O 20R S S 18R TDI ...

Page 6

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Pin Names Left Port Right Port Chip Enables - (Input R/W R/W Read/Write Enable - (Input ...

Page 7

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Truth Table I—Read/Write and Enable Control OE SEM ...

Page 8

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Recommended DC Operating Conditions with V DDQ Symbol Parameter Min. V Core Supply Voltage 3.15 DD (3) V I/O Supply Voltage 2.4 DDQ V Ground 0 SS (3) Input High ...

Page 9

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol Parameter ( Input Leakage Current Output Leakage Current LO (2) V (3.3V) Output ...

Page 10

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM AC Test Conditions (V Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load 50Ω DATA OUT Figure 1. AC Output Test load ...

Page 11

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol READ CYCLE t Read Cycle Time RC t Address Access Time AA (3) t Chip Enable Access Time ...

Page 12

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Waveform of Read Cycles ADDR CE OE BEn R/W DATA OUT BUSY OUT NOTES: 1. Timing depends on which signal is asserted last, OE BEn. 2. Timing depends ...

Page 13

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Timing Waveform of Write Cycle No. 1, R/W Controlled Timing ADDRESS OE ( SEM (9) BEn ( R/W DATA OUT DATA IN Timing Waveform of Write ...

Page 14

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Timing Waveform of Semaphore Read after Write Timing, Either Side VALID ADDRESS t SEM/BEn (1) I R/W OE NOTES for ...

Page 15

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range Symbol BUSY TIMING (M/S BUSY Access Time from Address Match t BAA BUSY Disable Time from Address ...

Page 16

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Timing Waveform of Write with Port-to-Port Read and BUSY (M ADDR "A" R/W "A" DATA IN "A" (1) t APS ADDR "B" BUSY "B" DATA OUT "B" NOTES: ...

Page 17

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Waveform of BUSY Arbitration Controlled by CE Timing (M ADDR "A" and "B" CE "A" (2) t APS CE "B" BUSY "B" Waveform of BUSY Arbitration Cycle Controlled ...

Page 18

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Waveform of Interrupt Timing ADDR "A" CE "A" R/W "A" INT "B" ADDR "B" CE "B" OE "B" INT "B" NOTES: 1. All timing is the same for left and ...

Page 19

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Truth Table IV — Address BUSY Arbitration Inputs Outputs ( 16L CE CE BUSY ( 16R MATCH H ...

Page 20

... IDT70V658 and 7FFE for IDT70V657)or 1FFFF (FFFF for IDT70V658 and 7FFF for IDT70V657) is user-defined since addressable SRAM location. If the interrupt function is not used, address locations 1FFFE (FFFE for IDT70V658 and 7FFE for IDT70V657) and 1FFFF (FFFF for IDT70V658 and 7FFF for IDT70V657) are not used as mail boxes, but as part of the random access memory ...

Page 21

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM How the Semaphore Flags Work The semaphore logic is a set of eight latches which are independent of the Dual-Port RAM. These latches can be used to pass a flag, ...

Page 22

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM JTAG Timing Specifications t JF TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, ...

Page 23

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Identification Register Definitions Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) NOTE: 1. Device ID for IDT70V658 is 0x30B. ...

Page 24

IDT70V659/58/57S High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Ordering Information XXXXX A 999 A Device Power Speed Package Type Notes: 1. Contact your local sales office for Industrial temp range in other speeds, packages and powers. 2. Green ...

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