MT90869AG Zarlink, MT90869AG Datasheet - Page 14

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

Pin Description
FP8i
C8i
CS
DS
R/W
A0 - A14
D0 - D15
DTA
TMS
TCK
TDi
TDo
TRST
RESET
Name
U14
W12
B11
A11
C11
D5, C6, A6, D7, C7,
B7, C8, B8, A8, D9,
B9, A9, D10, C10,
A10
V10, Y9, W9, V9,U9,
Y8, W8, V8, W7, V7,
U7, Y6, W6, V6, Y5,
W5
A13
D12
A14
B13
C13
B14
C12
Coordinates
Package
Frame Pulse Input (5 V Tolerant). This pin accepts the Frame Pulse signal. The
pulse width may be active for 122 ns or 244 ns at the frame boundary and the
Frame Pulse Width bit (FPW) of the Control Register must be set Low (default) for
a 122 ns and set High for a the 244 ns pulse condition.The device will
automatically detect whether an ST-BUS or GCI-BUS style frame pulse is applied.
Master Clock Input (5 V Tolerant). This pin accepts a 8.192 MHz clock. The
internal Frame Boundary is aligned with the rising edge of this clock. This rising
edge frame boundary alignment is controlled by the C8IPOL bit in the Control
Register as shown in Table 16 on page 51. The C8IPOL bit MUST be set to ONE
for the rising edge frame boundary to be detected correctly. Falling C8i edge frame
boundary alignment is not supported and should not be used.
Chip Select (5 V Tolerant). Active low input used by the microprocessor to enable
the microprocessor port access. This input is internally set low during a device
RESET.
Data Strobe (5 V Tolerant). This active low input works in conjunction with CS to
enable the microprocessor port read and write operations.
Read/Write (5 V Tolerant). This input controls the direction of the data bus lines
(D0-D15) during a microprocessor access.
Address 0 - 14 (5 V Tolerant). These pins form the 15-bit address bus to the
internal memories and registers.
A0 = LSB
Data Bus 0 - 15 (5 V Tolerant). These pins form the 16-bit data bus of the
microprocessor port.
D0 = LSB
Data Transfer Acknowledgment (5 V Tolerant). This active low output indicates
that a data bus transfer is complete. A pull-up resistor is required to hold a HIGH
level. (Max. I
Test Mode Select (5 V Tolerant with internal pull-up). JTAG signal that controls
the state transitions of the TAP controller.
Test Clock (5 V Tolerant). Provides the clock to the JTAG test logic.
Test Serial Data In (5 V Tolerant with internal pull-up). JTAG serial test
instructions and data are shifted in on this pin.
Test Serial Data Out (5 V Tolerant Three-state Output). JTAG serial data is
output on this pin on the falling edge of TCK. This pin is held in high impedance
state when JTAG is not enabled.
Test Reset (5 V Tolerant with internal pull-up) Asynchronously initializes the
JTAG TAP controller to the Test-Logic-Reset state. To be pulsed low during power-
up for JTAG testing. This pin must be held LOW for normal functional operation of
the device.
Device Reset (5 V Tolerant with internal pull-up). This input (active LOW)
asynchronously applies reset and synchronously releases reset to the device. In
the reset state, the outputs LSTo0 - 31 and BSTo0 - 31 are set to a high or high
impedance depending on the state of the LORS and BORS external control pins,
respectively. It clears the device registers and internal counters. This pin must stay
low for more than 2 cycles of input clock C8i for the reset to be invoked.
Zarlink Semiconductor Inc.
MT90869
OL
= 10 mA).
14
Description
Data Sheet