MT90869AG Zarlink, MT90869AG Datasheet - Page 57

• Manufacturer Part Number: MT90869AG
• Description: Switch Fabric 16K x 16K/8K x 8K 1.8V/3.3V 272-Pin BGA Tray
• Manufacturer: Zarlink

Specifications of MT90869AG

• Package: 272BGA
• Number Of Ports: 64
• Fabric Size: 16K x 16K|8K x 8K
• Switch Core: Non-Blocking|Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 1.8|3.3 V

13.5.1
These five bits define the delay from the bit boundary that the receiver uses to sample each input. Input bit delay
adjustment can range up to 7
This can be described as: LIDn(4:0) = (number of bits delay) / 4
For example, if LIDn(4:0) is set to 10011 (19), the input bit delay = 19 *
Table 22, “Local Input Bit Delay Programming Table,” on page 57, illustrates the bit delay selection.
0 (Default)
Data Rate
1 1/4
1 1/2
1 3/4
2 1/4
2 1/2
2 3/4
3 1/4
3 1/2
3 3/4
4 1/4
4 1/2
4 3/4
5 1/4
5 1/2
5 3/4
6 1/4
6 1/2
6 3/4
7 1/4
7 1/2
7 3/4
1/4
1/2
3/4
Local Input Delay Bits 4-0 (LID4 - LID0)
1
2
3
4
5
6
7
Table 22 - Local Input Bit Delay Programming Table
LID4
3
/
4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
bit periods forward, with resolution of
Zarlink Semiconductor Inc.
LID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
MT90869
Corresponding Delay Bits
57
LID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
/
1
4
/
4
bit period.
= 4
3
/
4.
LID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Data Sheet
LID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1