MT90840AP Zarlink, MT90840AP Datasheet
MT90840AP
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MT90840AP Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002-2007, Zarlink Semiconductor Inc. All Rights Reserved. Distributed Hyperchannel Switch MT90840AL1 MT90840AP1 MT90840APR1 • Guarantees frame integrity when switching nX64 wideband channels such as ISDN H0 channel • Provides external control lines allowing fast ...
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... Change Summary Changes from April 2006 to April 2007. Page, section, figure and table numbers refer to this current issue. Page Item 1 Ordering Information Box MT90840 Change Removed part numbers MT90840AL and MT90840AP from ordering information. 2 Zarlink Semiconductor Inc. Data Sheet ...
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... PPFTi/o 90 VSS VDD 100 PIN PQFP 92 PDi7 PDi6 94 PDi5 PDi4 96 PDi3 PDi2 98 PDi1 PDi0 100 VSS Figure 2 - Pin Connections Zarlink Semiconductor Inc. MT90840 74 VSS STo0 72 STo1 STo2 70 STo3 STo4 68 STo5 STo6 66 STo7 SPCKo 84 PIN PLCC 64 VSS VDD 62 TDO TMS 60 TCK TRST ...
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... Mbps applications, streams STi0-STi7 can be used, while for 8.192 Mbps, only streams STi0-STi3 are used (512 channel limit). These eight bidirectional lines can be programmed as inputs (default) or outputs on a per-channel basis. MT90840 Description 4 Zarlink Semiconductor Inc. Data Sheet . This pin must remain SS ...
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... MHz). See Per-Channel Functions section. 34-41 81-88 PDo7- Parallel Data Output Port (Output). These eight outputs carry the parallel port data bytes in the transmit direction and operate at data rates up to PDo0 19.44 Mbyte/s. MT90840 Description 5 Zarlink Semiconductor Inc. Data Sheet ...
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... In TM1 and TM4, this output is automatically placed in high impedance. For applications with the serial port running at 8.192 Mbps this output is not used, and an 8.192 MHz clock source must be supplied at C4/8R1 or C4/8R2. MT90840 Description 6 Zarlink Semiconductor Inc. Data Sheet ...
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... Functional Description The MT90840 Distributed Hyperchannel Switch is a large switching, multiplexing, and rate-adapting device. The MT90840 bridges serial-bus telecom components, using the Zarlink ST-BUS or other industry-standard serial buses, onto a higher speed “backbone”. Mixed data, voice and video signals can be time-interchanged or multiplexed from serial Time Division Multiplexed (TDM) streams onto a high speed parallel bus ...
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... Receive Path: parallel port input (PDi) to serial port output (STo), • Bypass and Parallel-Switching: PDi to PDo. In addition, Zarlink Message Mode capabilities allow the user to force data on TDM output time slots and to monitor TDM input time slots through the microprocessor port. The MT90840 has four main interfaces: • ...
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... MHz) Serial I/O ch.127 8 Mbps b3 Figure 3 - Serial Port Interface Functional Timing MT90840 Frame Boundary Established by F0 Ch. 31 Bit 0 Ch. 0 Bit 7 Ch. 63 Bit 0 Ch. 0 Bit 7 ch.127 ch.127 ch.127 ch Zarlink Semiconductor Inc. Data Sheet Ch. 0 Bit 6 Ch. 0 Bit 6 Ch. 0 Bit 5 ch ...
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... Connection Memory High holds the high-order bit(s) of the source address-value, and is also programmed to control per-channel functions such as output driver-enable and programmable control outputs. MT90840 Frame Boundary Established by PPFRi Ch. n Ch. 0 Frame Boundary Established by PPFTi/o Ch Zarlink Semiconductor Inc. Data Sheet Ch. 1 Ch. 2 Ch. 1 Ch. 2 ...
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... In Parallel Switching Mode (TM4) this is a switching path, and the Tx Path Connection Memory is programmed to switch parallel inputs to parallel outputs. For each parallel output channel control-address, the Tx Path Connection Memory is programmed with the 12-bit address-value of the desired parallel input channel. MT90840 11 Zarlink Semiconductor Inc. Data Sheet ...
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... This mode supports 512 serial input channels and 512 serial output channels. The serial clock for this mode is 8.192 MHz. Per-channel direction control in this mode is the same as the 2.048 Mbps balanced mode. MT90840 12 Zarlink Semiconductor Inc. Data Sheet ...
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... The user can further specify the features of the parallel TDM port, including: • the edge of the parallel port clock used to transmit data and PPFTo (see TCP bit in the TIM register), • the polarity of the Parallel Port Frame Transmit pulse PPFT (see PPFP bit in the GPM register), MT90840 13 Zarlink Semiconductor Inc. Data Sheet ...
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... TM1 and TM2 respectively. In all MT90840 timing modes, the throughput delay when performing time interchange functions of grouped channel data is constant, maintaining the frame integrity of the input and output data. MT90840 14 Zarlink Semiconductor Inc. Data Sheet ...
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... The TM1 Multiple-MT90840 sub-mode is not available for operation at 6.48 Mbyte/s. MT90840 MT90840 PCKR 8 STi/o 0-7 PPFRi STi0-7 STi/o 0-7 8 PDi0-7 STo0-7 8 kHz PCKT F0i PPFTo 4.096 C4/8R1 PDo0-7 or 8.192 MHz CPU 15 Zarlink Semiconductor Inc. Data Sheet ST-BUS Components 8 kHz Source PLL ...
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... MHz CPU MT90840 PPFT STi0-7 PDo0-7 STo0-7 PCKR SPCKo PDi0-7 F0o PPFRi C4/8R1 & 2 4.096 MHz or 8.192 MHz (8.192 MHz) PLL 16 Zarlink Semiconductor Inc. Data Sheet ST-BUS Components 8 kHz Source PLL TX Clock STi/o 0-7 8 STi/o 0-7 8 ST-BUS Components 4.096 MHz 8 kHz ...
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... TM2 MT90840s to share one timing source. The transmit parallel port outputs are always synchronized to PPFRi in TM2, so the multiple MT90840s can also be connected together on one parallel output bus. The TM2 Multiple-MT90840 sub-mode is not available for operation at 6.48 Mbyte/s. MT90840 17 Zarlink Semiconductor Inc. Data Sheet ...
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... C4/8R1 & 2 4.096 MHz or 8.192 MHz PLL C4/8R1 & 2 PPFT STi0-7 PDo0-7 STo0-7 PCKR SPCKo PDi0-7 F0i PPFRi SFDI = 1 MT90840 18 Zarlink Semiconductor Inc. Data Sheet CPU STi/o 0 STi/o 0-7 ST-BUS Components 4.096 MHz 8 kHz (8.192 MHz) 8 STi/o 0-7 STi/o 0-7 8 4.096 MHz ...
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... F0o 4.096 MHz PCKR SPCKo CPU Figure 7 - Timing Mode 3 Configuration Clock Reference Parallel Data Out MT90840 8 PDo0-7 PDi0 kHz REF PPFTo 8 kHz RX PPFRi PCKR CPU Figure 8 - Timing Mode 4 Configuration 19 Zarlink Semiconductor Inc. Data Sheet STi/o 0-7 STi/o 0-7 ST-BUS Components 8 ...
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... Dmin = 12 µ sec + µ sec + 2 frames + Transmission + ELD + frame = 262 µ sec + Transmission + ELD + 137.4 µ sec 20 Zarlink Semiconductor Inc. Data Sheet Total Throughput Delay µ sec + µ sec, Max. 258 µ sec µ sec + ELD + µ sec µ sec + µ ...
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... D = (7.7 + 117.3) = 375 µ sec + Min. 250 µ sec, Avg. 375 21 Zarlink Semiconductor Inc. Data Sheet Total Throughput Delay sec + 4 frames + 2 X Transmission + ELD + sec + 2 frames + 2 X Transmission + ELD + µ sec + 2 frames + µ sec, Max. 500 µ sec (Note 4) ...
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... Output Frame Boundary Established by PPFT Channel 2429 Channel 0 TPCM High, CTn bit TPCM High, CTn bit address 0 address 2429 DC=0 for STo 0 channel 1 MT90840 DC=1 for STo 0 channel 29 22 Zarlink Semiconductor Inc. Data Sheet Channel 1 TPCM High, CTn bit address 1 STo0 I/P O ...
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... Bits 7:5 select one of 8 streams. Bits 4:0 select one of 32 channels per stream. RPCM Output Address STo0, Ch0 000H CPU Port Addressing: STo0, Ch1 001H . CAR Address Bus . Stream Channel STo7, Ch30 0FEH 0FFH STo7, Ch31 23 Zarlink Semiconductor Inc. Data Sheet ...
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... Stream STi7, Ch30 0FEH STi7, Ch31 0FFH TPCM Contents STo0 (STi8), Ch0 100H Stream STo0 (STi8), Ch1 101H . Bits 8:5 select one of 16 streams. . Bits 4:0 select one of 32 channels per stream. 1FEH 1FFH 24 Zarlink Semiconductor Inc. Data Sheet Channel Channel ...
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... STi0, Ch0 000H CAR Address Bus STi0, Ch1 001H . Stream Channel STi7, Ch62 1FEH TPCM Contents: 1FFH STi7, Ch63 Channel Stream Bits 8:6 select one of 8 streams. Bits 5:0 select one of 64 channels per stream. 25 Zarlink Semiconductor Inc. Data Sheet Channel ...
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... CPU Port Addressing: STi0, Ch1 . 001H CAR Address Bus . Stream Channel STi3, Ch126 1FEH STi4, Ch127 1FFH TPCM Contents Stream Channel Bits 8:7 select one of 8 streams. Bits 6:0 select one of 128 channels per stream. 26 Zarlink Semiconductor Inc. Data Sheet ...
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... IRQ output will not be activated. However, the interrupt indication will still be provided in the ALS bits. MT90840 RPCM Output Address STo0, Ch0 000H CPU Port Addressing: STo0, Ch1 . 001H CAR Address Bus . Stream Channel STo3, Ch126 1FEH STo4, Ch127 1FFH 27 Zarlink Semiconductor Inc. Data Sheet ...
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... MT90840 # Type R/W Test (leave 00hx Phase Status (Low byte Phase Status (High 3 bits Zarlink Semiconductor Inc. Data Sheet Reset Value LOCATION (Hex) IMS Register 60 Control Register 00 TIM Register 00 GPM Register 00 ALS Register 0X 00 reserved reserved XX 0X reserved ...
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... This is performed automatically by the MT90840 with an internal correction event, which inverts the phase of the SPCKo output. In normal operation the correction happens once on initialization, and does not happen again as long as the C4/8 and PCKR clocks stay phase-locked. MT90840 29 Zarlink Semiconductor Inc. Data Sheet ...
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... If a stable C4/8 serial port clock is not available stable F0i frame is not available, use TM2 with Internal Clocks (INTCLK=1) to perform block-programming of RPCM. -2- If stable PPFRi framing is not available in TM2, disable the external gate driving PPFRi and use free-running framing to perform block-programming of TPCM (and/or Internal Clocks mode to block-program RPCM). MT90840 30 Zarlink Semiconductor Inc. Data Sheet ...
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... Boundary-Scan chain concurrent with the normal operation of the MT90840. MT90840 BOUNDARY -SCAN CELL(BSC) T BSC BSC TEST DATA IN (TDI) BSC BSC TEST CLOCK (TCK CORE LOGIC T R TEST MODE O SELECT (TMS BSC BSC BSC BSC TEST DATA OUT (TDO) R Figure Typical Boundary-Scan IC 31 Zarlink Semiconductor Inc. Data Sheet ...
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... This instruction is used to BYPASS the MT90840 while performing boundary-scan testing on other devices with scan registers in the same serial register chain. The MT90840 is allowed to function normally. This instruction is automatically loaded upon TRST, as specified in IEEE1149.1 32 Zarlink Semiconductor Inc. Data Sheet ...
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... Table 4 - Boundary-Scan Register 33 Zarlink Semiconductor Inc. Data Sheet Note first bit out enables pdo<0:7> outputs always enabled tied HIGH internally ‘pseudo’ open- ...
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... Cells 65:66 67:78 79:80 81 82:84 85:102 103:105 106:107 Please visit our web site at www.semicon.Zarlink.com to download a BSDL file for the MT90840. MT90840 Definition asale_in dsrdb_in wrb_in ad<7>_out, ad<7>_in ad<6>, ad<5>, ... ad<1> ad<0>_out, ad<0>_in ad_en sto<0>_en, sto<0>_out, sto<0>_in sto<1>, sto<2>, ... sto<6> sto<7>_en, sto<7>_out, sto< ...
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... STo pin to become an input. For applications at 4.096 and 8.192 Mbps, this bit should be LOW. Note: Bits 1 & 2 must be set the CPU. MT90840 PPS0 ODE 0 0 FDC Zarlink Semiconductor Inc. Data Sheet ...
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... MT90840 generating the PPFTo. One MT90840 in TM1 with PFDI LOW can control several MT80940s with PFDI HIGH. When PFDI is HIGH, PPFP in the GPM register must be set to the expected PPFTi polarity. Note: Bit 7 must be set the CPU. MT90840 C4/8R TCP INTCLK SFDI PFDI Zarlink Semiconductor Inc. Data Sheet ...
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... This bit can also be written low to force the end of the block-program operation. Note The CPU must maintain the required settings of the PPFP and SPFP bits when BPE is written. The DIN function and the BPE : function should not be used simultaneously. MT90840 BPD4 PPFP DIN SPFP BPE Zarlink Semiconductor Inc. Data Sheet ...
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... The interrupt source bits are latched, and remain high until cleared by the CPU. The interrupt source bits (ALS low nibble) are cleared by writing the mask bits (ALS high nibble), regardless of the data written. MT90840 MSK0 PPCE RXPAA TXPAA FSA Zarlink Semiconductor Inc. Data Sheet ...
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... HA bits and input address lines used to select channel in TPCM. HA11-HA7 + AD6-AD0 HA10-HA7 + AD6-AD0 HA9-HA7 + AD6-AD0 39 Zarlink Semiconductor Inc. Data Sheet HA bits and input address lines, or TPCM address bits, used to select the time slot. AD4-AD0 / AB4-AB0 (32 time slots) AD4-AD0 / AB4-AB0 (32 time slots) ...
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... MT90840 PSD4 PSD3 PSD2 PSD1 PSD0 PSD10 PSD9 PSD8 CTo2/ CTo3/ CTo1 AB8 AB9 AB11 AB10 Zarlink Semiconductor Inc. Data Sheet Register Address 8 (Low Byte) Register Address 9 (High 3-bits) (TX Path CM High) ...
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... SOURCE STREAM ADDRESSING AB5,AB6,AB7,AB8 ( streams) AB6, AB7, AB8 used to select streams AB7, AB8 used to select streams 41 Zarlink Semiconductor Inc. Data Sheet (TX Path CM Low) SOURCE CHANNEL ADDRESSING AB0 to AB4 used to select channels per stream AB0 to AB5 used to select channels per stream ...
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... The MT90840 bridges existing Zarlink ST-BUS components into a new networking environment where mixed data, voice and video signals can be time-interchanged or multiplexed from serial PCM streams onto serial high-speed time-division- multiplex (TDM) isochronous backbones operating at SONET rates such as 51 (STS-1) or 155 Mbps (STS-3) ...
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... T1 & E1 I/F Call Processing 155 Mbps Framing & Optics Up to 2400 TDM channels of user data MT896x Filter/Codec Filter/Codec MT8930 / 71 (2B+D) I/F ISO Ethernet MUX 43 Zarlink Semiconductor Inc. Data Sheet PSTN CTI SERVER CTI SERVER Interchassis Signalling (e.g. Zarlink’s Connection Master Software) ...
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... 2.8 4 0 Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0 °C -65 +125 unless otherwise stated. Units Test Conditions ° Units Test Conditions/Pins mA Outputs unloaded V TTL inputs (most pins) V TTL inputs (most pins) V Schmitt inputs V Schmitt inputs µA ...
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... Zarlink Semiconductor Inc. Data Sheet Test Conditions C4/8R1 or C4/8R2 19.44 MHz 60/40% duty- cycle clock at PCKR ns C4/8R1 input with 244 ns cycle C4/8R1 or C4/8R2 ns ns 19.44 MHz 60/40% duty- ns cycle clock at PCKR C4/8R1 input with min. ns 115 ns semi-cycle ...
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... C and are for design aid only: not guaranteed and not subject to production testing. Test Point Output Pin C L MT90840 ) unless otherwise stated. SS ‡ Sym. Min. Typ. Max sod t 28 stis stih Figure 17 - Output Test Load 46 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions C =30pF =30pF =30pF =150pF =30pF ...
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... Serial Port with Negative Polarity F0 (ST-BUS) t clk t t clkh clkl t sod bit 7, ch stis bit 7, ch frs frh t frw Serial Port with Positive Polarity F0 (GCI) 47 Zarlink Semiconductor Inc. Data Sheet t stih bit 7, ch. 0 bit 6, ch stih ...
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... Serial Port with Negative Polarity F0 (ST-BUS) t clk t t clkh clkl t sod bit 7, ch stis bit 7, ch Serial Port with Positive Polarity F0 (GCI) 48 Zarlink Semiconductor Inc. Data Sheet t stih bit 7, ch. 0 bit 6, ch stih ...
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... Figure 20 - Serial Port Timing for 4.096 Mbps Operation - TM2 (SFDi = 1) and TM1 MT90840 t clk t t clkh clkl t sod bit 7, ch. 0 bit 6, ch stis stih bit 7, ch frh t frw t clk t t clkh clkl t sod bit 7, ch. 0 bit 6, ch stis stih bit 7, ch frs frh t frw 49 Zarlink Semiconductor Inc. Data Sheet t t ...
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... Figure 21 - Serial Port Timing for 4.096 Mbps Operation - TM2 (SFDi = 0) and TM3 MT90840 t clk t t clkh clkl t sod bit 7, ch. 0 bit 6, ch stis stih bit 7, ch clk clkh clkl t sod bit 7, ch. 0 bit 6, ch stis stih bit7, ch Zarlink Semiconductor Inc. Data Sheet ...
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... C4/8 (ST-BUS) STo0-7 Hi-Z Valid Data STo0-7 Figure 23 - Per-Channel Tristate Characteristics at all Data Rates MT90840 t clk t t clkh clkl t sod bit 7, ch. 0 bit 6, ch stis stih bit frh frs t frw t za Valid Data t az Hi-Z 51 Zarlink Semiconductor Inc. Data Sheet ...
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... Frame Sync with Positive Polarity (SPFP = 1) t clk t t clkh clkl t sod bit 7, ch stis stih bit Frame Sync with Negative Polarity (SPFP = 0) 52 Zarlink Semiconductor Inc. Data Sheet bit 6, ch. 0 bit 6, ch. 0 ...
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... CTo corresponding to CTo corresponding to byte m+1 byte m byte m+1 CTo corresponding to byte m+1 t clk t t clkh clkl t sod byte PPFH PPFS 53 Zarlink Semiconductor Inc. Data Sheet TCP controls the clock-edge on which the output changes. TCP = 1 TCP = byte 1 tristate n = 2429, 2047, or 809 ...
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... PCKT/PCKR clock. Figure 27 - Parallel Port Transmit Timing (PFDI = 0, PPFT is an output) PCKR PDi0-7 PPFRi Figure 28 - Parallel Port Receive Timing MT90840 t clk t t clkh clkl t sod byte clkh clkl t clk t t stis stih Byte 1 Byte Zarlink Semiconductor Inc. Data Sheet t az byte 1 tristate ...
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... TCP = 0 TCP = 1 Figure 29 - Parallel Port in Timing Mode 4 55 Zarlink Semiconductor Inc. Data Sheet Units Test Conditions =30pF L C =50pF =30pF L C =50pF =30pF L C =50pF =30pF ...
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... Note: The MT90840 will correct phase relation in TM2 by inverting SPCKo w.r.t. C4/8R1 or C4/8R2. Figure 31 - Phase Variation Between C4 and PCKR Inputs for TM2 Operation MT90840 Ch. 3 Bit 0 (4 Mbps n-2 n Ch. 61 Bit 1 (4 Mbps Zarlink Semiconductor Inc. Data Sheet Ch. 4 Bit Ch. 61 Bit 0 ...
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... Zarlink Semiconductor Inc. Data Sheet Voltages are with respect to ground Test Units Conditions/Notes =150 pF on DTA, L and AD0- =30 pF ...
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... AD7 t alrd CS t rst alwr DTA Figure 32 - Intel/National Multiplexed Bus Timing MT90840 DATA t csr t csw t dsw t t ddr rdd t akd 58 Zarlink Semiconductor Inc. Data Sheet 2.0V 0.8V 2.0V 0.8V t csrw 2.0V 0.8V 2.0V 0.8V t dhr 2.0V 0.8V t dhw t akh 2.0V 0.8V ...
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... Zarlink Semiconductor Inc. Data Sheet ) unless SS Test Units Conditions/Notes =150 pF on DTA AD0- = =150 =150 pF =1kW = =150 =30 pF ...
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... Zarlink Semiconductor Inc. Data Sheet ) unless SS Test Units Conditions/Notes cycles + register t akd- cycles + register t akd- PCKT/R cycles + register t akd- cycles + ...
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... AD0-7 ADDRESS WR AD0-13 ADDRESS RD CS DTA Figure 33 - Motorola Multiplexed Bus Timing MT90840 t rws t dsh t adh DATA t css t ddr t akd 61 Zarlink Semiconductor Inc. Data Sheet 2.0V 0.8V t rwh 2.0V 0.8V 2.0V 0.8V t dhw 2.0V 0.8V t dhr 2.0V DATA 0.8V 2.0V 0.8V t csh t akh 2 ...
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... Symbol Min. Max. t 100 tclk t 40 tclkl t 40 tclkh t 2 disu t 33 dih t 2 mssu t 5 msh t 20 dod t 15 trst t 15 rst t rst Figure 35 - RESET Timing 62 Zarlink Semiconductor Inc. Data Sheet t tclk t tclkl t trst Units Test Conditions ...
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... Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned ...