MT90840AP Zarlink, MT90840AP Datasheet - Page 5

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Pin Description (continued)
28-31
34-41
84
21
22
23
Pin #
70-73
81-88
100
65
66
67
C4/8R1
C4/8R2
PDo7-
Name
CTo3-
PDo0
CTo0
F0i/o
Serial Clock Reference Input 1. When enabled by the C4/8R bit (high) in the TIM
Register, this input receives the 4.096 or 8.192 MHz serial port clock reference. If
the C4/8R bit is set low, or if the INTCLK bit is set high, this input is ignored by the
MT90840.
In Timing Mode 1 (TM1), or at 8.192 MHz, the C4/8 input is used directly to shift
data in and out of the serial port.
In Timing Mode 2 (TM2) at 4.096 MHz, the C4 input from an external clock source
(e.g. a PLL locked to an 8 kHz reference) is phase-corrected by the MT90840, and
used to generate the serial port SPCKo and F0 outputs.
In Timing Modes 3 and 4 (TM3 and TM4) this input is not used.
For more details on the use of this signal, see the description of Timing Mode 1
and Timing Mode 2.
Serial Port Frame Synchronization (Bidirectional). This 8 kHz frame pulse signal
indicates the TDM 125 µsec frame boundary on the serial data port. This pin is
compatible with both ST-BUS/MVIP and GCI formatted framing signals.
In TM1 this pin is an input, and the MT90840 senses the polarity of this frame
pulse and automatically adapts the serial data port timing to the applicable format
(ST-BUS or GCI).
In TM2 with SFDI =1 this signal is an input, and its expected format is determined
by the SPFP bit in the GPM Register.
In TM2 (with SFDI =0), and in TM3, this signal is an output, generated from the
internal timing and synchronized to the SPCKo output clock. The polarity of the F0
pulse is determined by the SPFP bit in the GPM Register.
In TM4 this pin is not used.
C4/8R2 Serial Clock Reference Input 2. When enabled by the C4/8R bit (low) in
the TIM Register, this input receives the 4.096 or 8.192 MHz serial port clock
reference. If the C4/8R bit is set high, or if the INTCLK bit is set high, this input is
ignored by the MT90840. (See pin description for C4/8R1.)
External Control Lines 3 to 0 (Output). Output signals generated from the
MT90840 Transmit Path Connection Memory (TPCM). The four serial CTo output
lines represent the contents of the four CT bits in the TPCM, and are clocked at the
parallel port rate (up to 19.44 MHz). See Per-Channel Functions section.
Parallel Data Output Port 7 to 0 (Output). These eight outputs carry the parallel
port data bytes in the transmit direction and operate at data rates up to
19.44 Mbyte/s.
Zarlink Semiconductor Inc.
MT90840
5
Description
Data Sheet