MT90840AP Zarlink, MT90840AP Datasheet - Page 43

• Manufacturer Part Number: MT90840AP
• Description: Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
• Manufacturer: Zarlink

Specifications of MT90840AP

• Package: 84PLCC
• Number Of Ports: 16
• Fabric Size: 512 x 2430|512 x 512|2.373K x 2.373K
• Switch Core: Non-Blocking
• Port Speed: 8.192|4.096|2.048 Mbps
• Operating Supply Voltage: 5 V

Today, transmission links operating at SONET rates utilize serial-to-parallel and parallel-to-serial converters (or
framers) which perform embedded framing functions and give the user access to the payload of the high speed
frame. The MT90840 provides an 8-bit bidirectional parallel data port which directly interfaces to a high-speed
framer parallel data interface, allowing designers to build distributed networking systems with interconnection
speeds up to 155 Mbps. Figure 16 shows an example of a distributed networking application in a CTI system.
The MT90840's clock synchronization and reference options allow many applications and topologies when
isochronous TDM backbones are required. Two major clock synchronization schemes provided by the MT90840
allow the serial port interface (ST-BUS) to provide the master clock and frame reference signals for the distributed
high speed backbone (master operation) or to derive the entire ST-BUS clock and frame reference signals from the
high speed backbone (slave operation). This type of synchronization scheme may be used in applications such as
the proposed MVIP multi-chassis level 3 interface (MC-3 system) utilizing point-to-point or point-to-multipoint
switching connections.
When the MT90840 operates in a ring application, the Parallel Data Bypass mode is provided to allow all or part of
the received input parallel data to be bypassed to the output parallel port feeding the ring back with the data which
is not destined for the local station. The data destined for the local station can be dropped through CPU
programming. In this mode, the CPU has full control of the outgoing bandwidth (from the serial interface to the high
speed link) so that it does not contend with the bypassed data.
CTI Server
Switching
BUS
e.g.; MVIP
LAN ADAPTER CARD
MT8985/6
EDX
Figure 16 - CTI Distributed Architecture Implemented with the MT90840
MT90810
MT90840
FMIC
MT90810
FMIC
ST-BUS
ST-BUS
MT8930 / 71
ISO Ethernet
ST-BUS
(2B+D) I/F
MUX
Filter/Codec
Filter/Codec
MT896x
MT8977/9079
T1 & E1 I/F
Framing &
Zarlink Semiconductor Inc.
Processing
155 Mbps
Optics
Call
MT90840
43
24/30B+D
Up to 2400 TDM
channels of user data
PSTN
SERVER
SERVER
Interchassis Signalling
(e.g. Zarlink’s Connection
Master Software)
CTI
CTI
Data Sheet