MT90840AP Zarlink, MT90840AP Datasheet - Page 23

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MT90840AP

Manufacturer Part Number
MT90840AP
Description
Switch Fabric 512 x 2430/512 x 512/2.373K x 2.373K 5V 84-Pin PLCC Tube
Manufacturer
Zarlink
Datasheet

Specifications of MT90840AP

Package
84PLCC
Number Of Ports
16
Fabric Size
512 x 2430|512 x 512|2.373K x 2.373K
Switch Core
Non-Blocking
Port Speed
8.192|4.096|2.048 Mbps
Operating Supply Voltage
5 V

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Manufacturer
Quantity
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Part Number:
MT90840AP
Manufacturer:
ZARLINK
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Quantity:
20 000
Serial Data Memory Addressing
The serial port mode determines the number of channels per stream, the number of streams, and the direction-
control operation. Therefore the way in which serial data is addressed in the internal memory space must change
with the serial port mode. Because of this, it is necessary to select the serial port mode (with DR1-0 and FDC in the
IMS register) before programming the Receive Path Connection Memory.
2.048 Mbps Balanced Mode
The 2.048 Mbps Balanced mode has 8 serial input and 8 serial output streams, and 32 channels per stream.
Therefore 3 bits are used to address the 8 streams, and 5 bits are used to address the 32 channels. Figure 11a
shows how the Transmit Path Data Memory is read in this mode, by the CPU, or by the Transmit Path Connection
Memory. Each of the 256 input channels is mapped to an address in the TPDM. CPU reads require the LSB (Least
Significant Bit) of the CAR Register, and the 7 LSBs of the address bus. The source-channel address-value written
in the TPCM requires 8 bits.
Figure 11b shows how the Receive Path Connection Memory is addressed by the CPU. Each of the 256 output
channels has a control-address in the RPCM. CPU accesses require the LSB of the CAR Register, and the 7 LSBs
of the address bus. When the DC bit for a specific output channel is LOW, that channel is output on the STi pin
rather than the STo pin, and the data at the STo pin is input to the TPDM. When the DC bit is HIGH, the output
channel appears at the normal STo pin.
Figure 11a - 2.048 Mbps Balanced Mode TPDM Addressing
Figure 11b - 2.048 Mbps Balanced Mode RPCM Addressing
Serial
Channel
Note: Only 256 memory
locations.
Note: Only 256 memory locations.
Serial
Channel
STi7, Ch30
STi7, Ch31
STo7, Ch30
STo7, Ch31
STi0, Ch0
STi0, Ch1
STo0, Ch0
STo0, Ch1
.
.
.
.
Output
Input
Zarlink Semiconductor Inc.
TPDM
Address
000H
001H
0FEH
0FFH
000H
001H
0FEH
0FFH
RPCM
Address
MT90840
23
CAR
CAR
CPU Port Addressing:
TPCM Contents:
Stream
Bits 7:5 select one of 8 streams.
Bits 4:0 select one of 32 channels
per stream.
CPU Port Addressing:
0
7 6 5
0
Stream
Stream
Address Bus
Address Bus
6 5 4 3 2 1 0
6 5 4 3 2 1 0
Channel
4 3 2 1 0
Channel
Channel
Data Sheet

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