LPC4350FET256,551 NXP Semiconductors, LPC4350FET256,551 Datasheet
LPC4350FET256,551
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LPC4350FET256,551 Summary of contents
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LPC4350/30/20/10 32-bit ARM Cortex-M4/M0 MCU 264 kB SRAM; Ethernet; two High-speed USBs; advanced configurable peripherals Rev. 2.1 — 23 September 2011 1. General description The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embedded applications which include an ARM ...
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... NXP Semiconductors JTAG and Serial Wire Debug (SWD), serial trace, eight breakpoints, and four watch points. Enhanced Trace Module (ETM) and Enhanced Trace Buffer (ETB) support. System tick timer. Cortex-M0 Processor core ARM Cortex-M0 co-processor capable of off-loading the main ARM Cortex-M4 application processor. ...
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... NXP Semiconductors LCD controller with DMA support and a programmable display resolution 1024H 768V. Supports monochrome and color STN panels and TFT color panels; supports 1/2/4/8 bpp Color Look-Up Table (CLUT) and 16/24-bit direct pixel mapping. Secure Digital Input Output (SD/MMC) card interface. ...
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... NXP Semiconductors Processor wake-up from Sleep mode via wake-up interrupts from various peripherals. Wake-up from Deep-sleep, Power-down, and Deep power-down modes via external interrupts and interrupts generated by battery powered blocks in the RTC power domain. Brownout detect with four separate thresholds for interrupt and forced reset. ...
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... NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name LPC4350FET256 LBGA256 LPC4350FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls LPC4350FBD208 LQFP208 LPC4330FET256 LBGA256 LPC4330FET180 TFBGA180 Thin fine-pitch ball grid array package; 180 balls TFBGA100 Plastic thin fine-pitch ball grid array package; 100 balls; body 9 9 0.7 mm ...
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... NXP Semiconductors 5. Block diagram LPC4350/30/20/10 TEST/DEBUG INTERFACE ARM CORTEX-M4 GPDMA BRIDGE 0 BRIDGE 1 WWDT MOTOR CONTROL USART0 (1) PWM UART1 SSP0 TIMER0 C_CAN1 TIMER1 SCU GPIO INTERRUPTS GPIO GROUP0 INTERRUPT GPIO GROUP1 INTERRUPT = connected to GPDMA (1) Not available on all parts (see Fig 1. LPC4350/30/20/10 Block diagram ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning LPC4350/30FET256 ball A1 index area Transparent top view Fig 2. Pin configuration LBGA256 package Fig 4. LPC4350_30_20_10 Objective data sheet 002aaf813 Fig 3. ball A1 index area Pin configuration TFBGA100 package All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 23 September 2011 ...
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... NXP Semiconductors 1 LPC4350FBD208 52 Fig 5. Pin configuration LQFP208 package Fig 7. 6.2 Pin description On the LPC4350/30/20/10, digital pins are grouped into 16 ports, named and PA to PF, with pins used per port. Each digital pin may support up to eight different digital functions, including General Purpose I/O (GPIO), selectable through the System Configuration Unit (SCU) registers ...
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... NXP Semiconductors Table 3. Pin description LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol Multiplexed digital pins P0_0 P0_1 P1_0 LPC4350_30_20_10 Objective data sheet [ I/O GPIO0[0] — General purpose digital input/output pin. I/O SSP1_MISO — Master In Slave Out for SSP1. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P1_1 P1_2 P1_3 P1_4 LPC4350_30_20_10 Objective data sheet [ I/O GPIO0[8] — General purpose digital input/output pin. O I/O EMC_A6 — External memory address line 6. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P1_5 P1_6 P1_7 LPC4350_30_20_10 Objective data sheet [ I/O GPIO1[8] — General purpose digital input/output pin I/O SSP1_SSEL — Slave Select for SSP1. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P1_8 P1_9 P1_10 P1_11 LPC4350_30_20_10 Objective data sheet [ I/O GPIO1[1] — General purpose digital input/output pin I/O EMC_D1 — External memory data line 1. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P1_12 P1_13 R10 x H8 P1_14 R11 x J8 P1_15 T12 x K8 LPC4350_30_20_10 Objective data sheet [ I/O GPIO1[5] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P1_16 P1_17 M8 x H10 93 P1_18 N12 x J10 LPC4350_30_20_10 Objective data sheet [ I/O GPIO0[3] — General purpose digital input/output pin. I I/O SGPIO3 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P1_19 M11 x K9 P1_20 M10 x K10 100 70 P2_0 T16 x G10 108 75 LPC4350_30_20_10 Objective data sheet [ I/O SSP1_SCK — Serial clock for SSP1. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P2_1 N15 x G7 P2_2 M15 x F5 P2_3 J12 x D8 LPC4350_30_20_10 Objective data sheet [3] 116 I/O SGPIO5 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P2_4 K11 x D9 P2_5 K14 x D10 131 91 P2_6 K16 x G9 LPC4350_30_20_10 Objective data sheet [4] 128 I/O SGPIO13 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P2_7 H14 x C10 138 96 P2_8 J16 x C6 P2_9 H16 x B10 144 102 70 P2_10 G16 x E8 LPC4350_30_20_10 Objective data sheet [ I/O GPIO0[7] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P2_11 F16 x A9 P2_12 E15 x B9 P2_13 C16 x A10 156 108 75 LPC4350_30_20_10 Objective data sheet [3] 148 105 I/O GPIO1[11] — General purpose digital input/output ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P3_0 F13 x A8 P3_1 G11 x F7 P3_2 F11 x G6 LPC4350_30_20_10 Objective data sheet [3] 161 112 I/O I2S0_RX_SCK — I2S transmit clock driven by O I/O I2S0_TX_SCK — ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P3_3 B14 x A7 P3_4 A15 x B8 P3_5 C12 x B7 LPC4350_30_20_10 Objective data sheet [5] 169 118 I/O SPI_SCK — Serial clock for SPI. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P3_6 B13 x C7 P3_7 C11 x D7 P3_8 C10 x E7 LPC4350_30_20_10 Objective data sheet [3] 174 122 I/O GPIO0[6] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P4_0 P4_1 P4_2 P4_3 LPC4350_30_20_10 Objective data sheet [ I/O GPIO2[0] — General purpose digital input/output pin I/O U3_UCLK — Serial clock input/output for USART3 in ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P4_4 P4_5 P4_6 LPC4350_30_20_10 Objective data sheet [ I/O GPIO2[4] — General purpose digital input/output pin I/O U3_DIR — RS-485/EIA-485 output enable/direction I/O SGPIO10 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P4_7 P4_8 P4_9 LPC4350_30_20_10 Objective data sheet [ <tbd O > I/O I2S1_TX_SCK — Receive Clock driven by the I/O I2S0_TX_SCK — Receive Clock driven by the ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P4_10 P5_0 P5_1 P5_2 LPC4350_30_20_10 Objective data sheet [ I/O GPIO5[14] — General purpose digital input/output O - I/O SGPIO15 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P5_3 P5_4 P5_5 P10 x - P5_6 T13 x - LPC4350_30_20_10 Objective data sheet [ I/O GPIO2[12] — General purpose digital input/output I I/O EMC_D15 — External memory data line 15. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P5_7 R12 x - P6_0 M12 x H7 P6_1 R15 x G5 LPC4350_30_20_10 Objective data sheet [ I/O GPIO2[7] — General purpose digital input/output pin. O I/O EMC_D11 — External memory data line 11. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P6_2 L13 x J9 P6_3 P15 x - P6_4 R16 x F6 LPC4350_30_20_10 Objective data sheet [3] 111 I/O GPIO3[1] — General purpose digital input/output pin. O I/O U0_DIR — RS-485/EIA-485 output enable/direction I/O I2S0_RX_SDA — ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P6_5 P16 x F9 P6_6 L14 x - P6_7 J13 x - LPC4350_30_20_10 Objective data sheet [3] 117 I/O GPIO3[4] — General purpose digital input/output pin [3] 119 I/O GPIO0[5] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P6_8 H13 x - P6_9 J15 x F8 P6_10 H15 x - P6_11 H12 x C9 LPC4350_30_20_10 Objective data sheet [3] 125 I/O EMC_A14 — External memory address line 14. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P6_12 G15 x - P7_0 B16 x - P7_1 C14 x - LPC4350_30_20_10 Objective data sheet [3] 145 103 - I; PU I/O GPIO2[8] — General purpose digital input/output pin [3] 158 110 - I ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P7_2 A16 x - P7_3 C13 x - P7_4 LPC4350_30_20_10 Objective data sheet [3] 165 115 - I; PU I/O GPIO3[10] — General purpose digital input/output I I/O I2S0_TX_SDA — I2S transmit data driven by the ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P7_5 P7_6 P7_7 LPC4350_30_20_10 Objective data sheet [6] 191 133 - I; PU I/O GPIO3[13] — General purpose digital input/output [3] 194 134 - I; PU I/O GPIO3[14] — General purpose digital input/output ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P8_0 P8_1 P8_2 P8_3 LPC4350_30_20_10 Objective data sheet [ I/O GPIO4[0] — General purpose digital input/output pin I/O SGPIO8 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P8_4 P8_5 P8_6 P8_7 LPC4350_30_20_10 Objective data sheet [ I/O GPIO4[4] — General purpose digital input/output pin. I/O USB1_ULPI_D1 — ULPI link bidirectional data line 1. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P8_8 P9_0 P9_1 LPC4350_30_20_10 Objective data sheet [ [ I/O GPIO4[12] — General purpose digital input/output I/O SGPIO0 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P9_2 P9_3 P9_4 N10 x - LPC4350_30_20_10 Objective data sheet [ I/O GPIO4[14] — General purpose digital input/output I/O I2S0_TX_SDA — I2S transmit data driven by the I I/O SGPIO2 — ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol P9_5 P9_6 L11 x - PA_0 L12 x - LPC4350_30_20_10 Objective data sheet [ I/O GPIO5[18] — General purpose digital input/output O I/O SGPIO3 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PA_1 J14 x - PA_2 K15 x - PA_3 H11 x - PA_4 G13 x - LPC4350_30_20_10 Objective data sheet [4] 134 - - I; PU I/O GPIO4[8] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PB_0 B15 x - PB_1 A14 x - PB_2 B12 x - PB_3 A13 x - LPC4350_30_20_10 Objective data sheet [3] 164 - - I/O GPIO5[20] — General purpose digital input/output - - - [3] 175 - - I/O GPIO5[21] — General purpose digital input/output ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PB_4 B11 x - PB_5 A12 x - PB_6 LPC4350_30_20_10 Objective data sheet [3] 180 - - I/O USB1_ULPI_D5 — ULPI link bidirectional data line I/O GPIO5[24] — General purpose digital input/output ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PC_0 PC_1 PC_2 LPC4350_30_20_10 Objective data sheet [ I/O ENET_RX_CLK — Ethernet Receive Clock (MII I/O SD_CLK — SD/MMC card clock I/O USB1_ULPI_D7 — ULPI link bidirectional data line 7. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PC_3 PC_4 PC_5 PC_6 LPC4350_30_20_10 Objective data sheet [ I/O USB1_ULPI_D5 — ULPI link bidirectional data line I/O GPIO6[2] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PC_7 PC_8 PC_9 PC_10 LPC4350_30_20_10 Objective data sheet [ I/O USB1_ULPI_D1 — ULPI link bidirectional data line I/O GPIO6[6] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PC_11 PC_12 PC_13 LPC4350_30_20_10 Objective data sheet [ I/O GPIO6[10] — General purpose digital input/output - - I/O SD_DAT4 — SD/MMC data bus line 4. [3] ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PC_14 PD_0 PD_1 PD_2 LPC4350_30_20_10 Objective data sheet [ I/O GPIO6[13] — General purpose digital input/output I/O SGPIO13 — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PD_3 PD_4 PD_5 PD_6 LPC4350_30_20_10 Objective data sheet [ I/O EMC_D17 — External memory data line 17. - I/O GPIO6[17] — General purpose digital input/output ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PD_7 PD_8 PD_9 T11 - - PD_10 P11 - - LPC4350_30_20_10 Objective data sheet [ I/O EMC_D21 — External memory data line 21. - I/O GPIO6[21] — General purpose digital input/output ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PD_11 PD_12 N11 x - PD_13 T14 x - LPC4350_30_20_10 Objective data sheet [ I/O GPIO6[25] — General purpose digital input/output I/O USB1_ULPI_D0 — ULPI link bidirectional data line 0. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PD_14 R13 x - PD_15 T15 x - PD_16 R14 x - PE_0 P14 x - LPC4350_30_20_10 Objective data sheet [ I/O GPIO6[28] — General purpose digital input/output - O - [3] 101 - - I/O EMC_A17 — External memory address line 17. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PE_1 N14 x - PE_2 M14 x - PE_3 K12 x - PE_4 K13 x - LPC4350_30_20_10 Objective data sheet [3] 112 - - I/O EMC_A19 — External memory address line 19. I/O GPIO7[1] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PE_5 N16 - - PE_6 M16 - - PE_7 F15 - - PE_8 F14 - - LPC4350_30_20_10 Objective data sheet [3] 122 - - I/O EMC_D24 — External memory data line 24. I/O GPIO7[5] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PE_9 E16 - - PE_10 E14 - - PE_11 D16 - - PE_12 D15 - - LPC4350_30_20_10 Objective data sheet [3] 152 - - I/O EMC_D28 — External memory data line 28. I/O GPIO7[9] — General purpose digital input/output pin. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PE_13 G14 - - PE_14 C15 - - PE_15 E13 - - LPC4350_30_20_10 Objective data sheet [ I/O I2C1_SDA — I/O GPIO7[13] — General purpose digital input/output - - - [ I/O GPIO7[14] — General purpose digital input/output ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PF_0 D12 - - PF_1 E11 - - PF_2 D11 - - PF_3 E10 - - LPC4350_30_20_10 Objective data sheet [3] 159 - - I;IA I/O SSP0_SCK — Serial clock for SSP0 [ I/O SSP0_SSEL — Slave Select for SSP0. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PF_4 D10 x H4 PF_5 PF_6 LPC4350_30_20_10 Objective data sheet [3] 172 120 83 I;IA I/O SSP1_SCK — Serial clock for SSP1 I/O I2S0_RX_SCK — I2S transmit clock driven by ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PF_7 PF_8 PF_9 LPC4350_30_20_10 Objective data sheet [6] 193 - - I/O U3_BAUD — <tbd> for USART3. I/O SSP1_MOSI — Master Out Slave in for SSP1. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol PF_10 PF_11 Clock pins CLK0 LPC4350_30_20_10 Objective data sheet [6] 205 - I/O GPIO7[24] — General purpose digital input/output - [6] 207 - 100 I/O GPIO7[25] — General purpose digital input/output ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol CLK1 T10 x - CLK2 D14 x K6 CLK3 P12 x - Debug pins DBGEN TCK/SWDCLK TRST TMS/SWDIO TDO/SWO LPC4350_30_20_10 Objective data sheet [ [5] 141 I/O SD_CLK — SD/MMC card clock. ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol TDI USB0 pins USB0_DP USB0_DM USB0_VBUS USB0_ID USB0_RREF USB1 pins USB1_DP F12 x E9 USB1_DM G12 x E10 130 C-bus pins I2C0_SCL L15 x D6 ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol ADC0_5 ADC1_5 ADC0_6 ADC1_6 ADC0_7 ADC1_7 RTC RTC_ALARM A11 x C3 RTCX1 RTCX2 Crystal oscillator pins XTAL1 XTAL2 Power and ground pins USB0_VDDA ...
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... NXP Semiconductors Table 3. Pin description …continued LCD, Ethernet, USB0, and USB1 functions are not available on all parts. See Symbol VDDIO D7, x F10, E12, K5 F7, F8, G10, H10, J6, J7, K7, L9, L10, N7, N13 VDD - - - VSS G9 H7, J10, J11, K8 VSSIO C4, x C8, D13, D4, G6, D5, G7, G8, ...
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... NXP Semiconductors [ tolerant pad with 15 ns glitch filter providing high-speed digital I/O functions with TTL levels and hysteresis. [ tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output. When configured as a ADC input or DAC output, the pin is not 5 V tolerant and the digital section of the pad must be disabled by setting the pin to an input function and disabling the pull-up resistor through the pin’ ...
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... NXP Semiconductors 7. Functional description 7.1 Architectural overview The ARM Cortex-M4 includes three AHB-Lite buses: the system bus, the I-code bus, and the D-code bus. The I-code and D-code core buses allow for concurrent code and data accesses from different slave ports. ...
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... NXP Semiconductors 7.5 AHB multilayer matrix TEST/DEBUG TEST/DEBUG INTERFACE INTERFACE ARM ARM CORTEX-M4 CORTEX-M0 System I- D- bus code code bus bus AHB MULTILAYER MATRIX = master-slave connection Fig 8. AHB multilayer matrix master and slave connections 7.6 Nested Vectored Interrupt Controller (NVIC) The NVIC is an integral part of the Cortex-M4. The tight coupling to the CPU allows for low interrupt latency and efficient processing of late arriving interrupts ...
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... NXP Semiconductors • Software interrupt generation. 7.6.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. 7.7 Event router The event router combines various internal signals, interrupts, and the external interrupt ...
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... NXP Semiconductors 7.11 In-System Programming (ISP) In-System programming (ISP) is programming or reprogramming the on-chip SRAM memory, using the boot loader software and the USART0 serial port. This can be done when the part resides in the end-user board. ISP allows to load data into on-chip SRAM and execute code from on-chip SRAM ...
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... NXP Semiconductors Table 4. Boot mode when OTP BOOT_SRC bits are programmed Boot mode BOOT_SRC BOOT_SRC bit 3 bit 2 USB1 0 1 SPI (SSP USART3 1 0 [1] The boot loader programs the appropriate pin function at reset to boot using either SSP0 or SPIFI. Table 5. Boot mode when OPT BOOT_SRC bits are zero ...
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... NXP Semiconductors 0x2000 0000 16 MB static external memory CS3 0x1F00 0000 16 MB static external memory CS2 0x1E00 0000 16 MB static external memory CS1 0x1D00 0000 16 MB static external memory CS0 0x1C00 0000 reserved 0x1800 0000 SPIFI data 0x1400 0000 reserved 0x1041 0000 ...
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LPC4350/30/20/10 0x400F 0000 reserved 0x400E 5000 APB3 ADC1 0x400E 4000 peripherals ADC0 0x400E 3000 C_CAN0 0x400E 2000 DAC 0x400E 1000 I2C1 0x400E 0000 0x400C 8000 GIMA 0x400C 7000 QEI 0x400C 6000 APB2 SSP1 0x400C 5000 peripherals timer3 0x400C 4000 timer2 ...
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... NXP Semiconductors 7.14 Security features 7.14.1 AES decryption engine The hardware AES engine can decode data using the AES algorithm. 7.14.1.1 Features • Decoding of external flash data connected to the quad SPI Flash Interface (SPIFI) and other external boot sources. • Secure storage of decryption keys. ...
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... NXP Semiconductors • eight GPIO pins can be selected from all GPIO pins to create an edge- or level-sensitive GPIO interrupt request (GPIO interrupts). • Two GPIO group interrupts can be triggered by any pin or pins in each port (GPIO group0 and group1 interrupts). 7.16 Configurable digital peripherals 7 ...
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... NXP Semiconductors 7.16.2 Serial GPIO (SGPIO) The Serial GPIOs offer standard GPIO functionality enhanced with features to accelerate serial stream processing. 7.16.2.1 Features • Each SGPIO input/output slice can be used to perform a serial to parallel or parallel to serial data conversion. • 16 SGPIO input/output slices each with a 32-bit FIFO that can shift the input value from a pin or an output value to a pin with every cycle of a shift clock. • ...
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... NXP Semiconductors • Internal four-word FIFO per channel. • Supports 8, 16, and 32-bit wide transactions. • Big-endian and little-endian support. The DMA Controller defaults to little-endian mode on reset. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. ...
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... NXP Semiconductors 7.17.4.1 Features • Dynamic memory interface support including single data rate SDRAM. • Asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode. • Low transaction latency. • Read and write buffers to reduce latency and to improve performance. ...
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... NXP Semiconductors • This module has its own, integrated DMA engine. • USB interface electrical test software included in ROM USB stack. 7.17.6 High-speed USB Host/Device interface with ULPI (USB1) Remark: The USB1 controller is available on parts LPC4350/30. See The USB1 interface can operate as a full-speed USB Host/Device interface or can connect to an external ULPI PHY for High-speed operation ...
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... NXP Semiconductors • 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support. • bits-per-pixel (bpp) palettized displays for monochrome STN. • bpp palettized color displays for color STN and TFT. • 16 bpp true-color non-palettized for color STN and TFT. ...
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... NXP Semiconductors 7.18.1.1 Features • Maximum UART data bit rate of <tbd> MBit/s. • Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • ...
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... NXP Semiconductors 7.18.3.1 Features • Maximum SPI data bit rate <tbd> • Compliant with SPI specification • Synchronous, serial, full duplex communication • Combined SPI master and slave • Maximum data bit rate of one eighth of the input clock rate • 8 bits to 16 bits per transfer 7 ...
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... NXP Semiconductors • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ...
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... NXP Semiconductors 7.18.7.1 Features • Conforms to protocol version 2.0 parts A and B. • Supports bit rate Mbit/s. • Supports 32 Message Objects. • Each Message Object has its own identifier mask. • Provides programmable FIFO mode (concatenation of Message Objects). • Provides maskable interrupts. ...
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... NXP Semiconductors PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. 7.19.3 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts angular displacement into two pulse signals ...
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... NXP Semiconductors 7.19.5.1 Features • Internally resets chip if not periodically reloaded during the programmable time-out period. • Optional windowed operation requires reload to occur between a minimum and maximum time period, both programmable. • Optional warning interrupt can be generated at a programmable time prior to watchdog time-out. • ...
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... NXP Semiconductors 7.21 Peripherals in the RTC power domain 7.21.1 RTC The Real Time Clock (RTC set of counters for measuring time when system power is on, and optionally when it is off. It uses very little power when its registers are not being accessed by the CPU, especially reduced power modes. The RTC is clocked by a separate 32 kHz oscillator that produces internal time reference ...
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... NXP Semiconductors modes. By default function 0 is selected for all pins with pull-up enabled. Analog I/Os like one set of the ADC and the DAC pins as well as most USB functions reside on separate pins and are not controlled through the SCU. 7.22.3 Clock Generation Unit (CGU) The Clock Generator Unit (CGU) generates several base clocks ...
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... NXP Semiconductors 7.22.8 Reset Generation Unit (RGU) The RGU allows generation of independent reset signals for individual blocks and peripherals on the LPC4350/30/20/10. 7.22.9 Power control The LPC4350/30/20/10 feature several independent power domains to control power to the core and the peripherals (see alarm timer, the CREG block, the OTP controller, the back-up registers, and the event router) are located in the RTC power-domain which can be powered by a battery supply or the main regulator ...
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... NXP Semiconductors The LPC4350/30/20/10 can wake up from Deep-sleep, Power-down, and Deep power-down modes via the WAKEUP[3:0] pins and interrupts generated by battery powered blocks in the RTC power domain. 7.23 Serial Wire Debug/JTAG Debug and trace functions are integrated into the ARM Cortex-M4. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions ...
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... NXP Semiconductors 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V regulator supply voltage (3.3 V) DD(REG)(3V3) V input/output supply voltage DD(IO) V analog supply voltage (3.3 V) DDA(3V3) V battery supply voltage BAT V polyfuse programming voltage prog(pf) ...
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... NXP Semiconductors 9. Thermal characteristics The average chip junction temperature, T equation amb • T amb • R th(j-a) • The internal power dissipation is the product of I the I/O pins is often small and many times can be negligible. However it can be significant in some applications. Table 7. Thermal characteristics ...
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... NXP Semiconductors 10. Static characteristics Table 8. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Supply pins V input/output supply DD(IO) voltage V regulator supply voltage DD(REG)(3V3) (3 analog supply voltage DDA(3V3) (3 battery supply voltage BAT I regulator supply current DD(REG)(3V3) (3 ...
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... NXP Semiconductors Table 8. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Digital pins - normal drive strength I LOW-level input current HIGH-level input IH current I OFF-state output OZ current V input voltage I V output voltage O V HIGH-level input IH voltage V LOW-level input voltage ...
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... NXP Semiconductors Table 8. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Digital pins - high drive strength I LOW-level input current HIGH-level input IH current I OFF-state output OZ current V input voltage I V output voltage O V HIGH-level input IH voltage V LOW-level input voltage ...
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... NXP Semiconductors Table 8. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Oscillator pins V input voltage on pin i(XTAL1) XTAL1 V output voltage on pin o(XTAL2) XTAL2 USB pins V common-mode input IC voltage V differential input voltage i(dif) Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. ...
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... NXP Semiconductors 10.1 Electrical pin characteristics Fig 12. Typical HIGH-level output voltage V Fig 13. Typical LOW-level output current I LPC4350_30_20_10 Objective data sheet <tbd> Conditions 3.3 V; standard port pins. DD(REG)(3V3) DD(IO ( <tbd> Conditions 3.3 V; standard port pins. DD(REG)(3V3) DD(IO) All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors Fig 14. Typical pull-up current I Fig 15. Typical pull-down current I LPC4350_30_20_10 Objective data sheet <tbd> Conditions 3.3 V; standard port pins. DD(REG)(3V3) DD(IO) versus input voltage ( <tbd> Conditions 3.3 V; standard port pins. DD(REG)(3V3) DD(IO) versus input voltage V pd All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 10.2 Power consumption Fig 16. Typical supply current versus regulator supply voltage V Fig 17. Typical supply current versus temperature in active mode LPC4350_30_20_10 Objective data sheet <tbd> Conditions: <tbd>. mode <tbd> Conditions: <tbd>. All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors Fig 18. Typical supply current versus temperature in Sleep mode Fig 19. Typical supply current versus temperature in Deep-sleep mode LPC4350_30_20_10 Objective data sheet <tbd> Conditions: <tbd> ( <tbd> Conditions: <tbd> All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 23 September 2011 ...
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... NXP Semiconductors Fig 20. Typical supply current versus temperature in Power-down mode Fig 21. Typical supply current versus temperature in Deep power-down mode LPC4350_30_20_10 Objective data sheet 32-bit ARM Cortex-M4/M0 microcontroller <tbd> ( <tbd> All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 23 September 2011 ...
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... NXP Semiconductors Table amb Peripheral <tbd> Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [1] voltages. LPC4350_30_20_10 Objective data sheet Power consumption for individual peripherals 3.3 V. DD(REEG)(3V3) All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 11. Dynamic characteristics 11.1 Digital I/O and CLKOUT pins, oscillator, PLL, and C_CAN Table 10. Dynamic characteristics: Digital I/O and CLKOUT pins, oscillator, PLL, and C_CAN over specified ranges; all voltages are measured with respect to ground; positive currents flow into the ...
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... NXP Semiconductors Fig 22. I/O delay versus V Fig 23. I/O delay versus V 11.2 External clock Table 11. amb Symbol Parameter f osc T cy(clk) t CHCX t CLCX t CLCH t CHCL LPC4350_30_20_10 Objective data sheet <tbd> for digital I/O pins DD(IO ( <tbd> for CLKOUT pin DD(IO) Dynamic characteristic: external clock ...
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... NXP Semiconductors [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. Fig 24. External clock timing (with an amplitude of at least V LPC4350_30_20_10 Objective data sheet 32-bit ARM Cortex-M4/M0 microcontroller ...
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... NXP Semiconductors 11.3 IRC and RTC oscillators Table 12. amb Symbol f osc(RC) f i(RTC) [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. Fig 25. Internal RC oscillator frequency versus temperature 2 11 ...
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... NXP Semiconductors Table 13. Dynamic characteristic: I [ +85 C. amb Symbol Parameter t LOW period of the SCL clock LOW t HIGH period of the SCL clock HIGH t data hold time HD;DAT t data set-up time SU;DAT [1] Parameters are valid over operating temperature range unless otherwise specified. ...
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... NXP Semiconductors SDA SCL SCL 2 Fig 26. I C-bus pins clock timing 2 11.5 I S-bus interface Table 14. amb Symbol common to input and output output t v(Q) input t su(D) t h(D) [1] CCLK = 100 MHz; peripheral clock to the I 1600 ns, corresponds to the SCK signal in the I LPC4350_30_20_10 Objective data sheet t SU ...
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... NXP Semiconductors I2S_TX_SCK I2S_TX_SDA I2S_TX_WS Fig 27. I I2S_RX_SCK I2S_RX_SDA I2S_RX_WS Fig 28. I LPC4350_30_20_10 Objective data sheet T cy(clk v(Q) t v(Q) 2 S-bus timing (transmit) T cy(clk S-bus timing (receive) All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 23 September 2011 LPC4350/30/20/10 32-bit ARM Cortex-M4/M0 microcontroller ...
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... NXP Semiconductors 11.6 SSP interface Table 15. Dynamic characteristics: SSP pins in SPI mode Symbol Parameter T PCLK cycle time cy(PCLK) T clock cycle time cy(clk) SSP master t data set-up time DS t data hold time DH t data output valid time v(Q) t data output hold time ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 29. SSP master timing in SPI mode LPC4350_30_20_10 Objective data sheet T cy(clk) t v(Q) DATA VALID MOSI MISO DATA VALID t v(Q) DATA VALID MOSI t DATA VALID MISO All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 23 September 2011 ...
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... NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 30. SSP slave timing in SPI mode 11.7 USART3 IrDA Table 16. Dynamic characteristics: USART3 IrDA Symbol Parameter t transmit rise time r(tx) t transmit fall time f(tx) IrDA TX data Fig 31. USART3 IrDA transmit timing LPC4350_30_20_10 Objective data sheet ...
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... NXP Semiconductors IrDA RX data RX data Fig 32. USART3 IrDA receive timing LPC4350_30_20_10 Objective data sheet bit time start All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 23 September 2011 LPC4350/30/20/10 32-bit ARM Cortex-M4/M0 microcontroller 16× clock delay data bits UART frame © ...
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... NXP Semiconductors 11.8 External memory interface Table 17. Dynamic characteristics: Static external memory interface pF amb [1] Symbol Parameter [2] Read cycle parameters t CS LOW to address valid CSLAV time t CS LOW to OE LOW time CSLOEL t CS LOW to BLS LOW time CSLBLSL t OE LOW to OE HIGH time ...
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... NXP Semiconductors Table 17. Dynamic characteristics: Static external memory interface pF amb [1] Symbol Parameter t BLS LOW to BLS HIGH time WR BLSLBLSH t BLS HIGH to end of write BLSHEOW time t BLS HIGH to data invalid BLSHDNV time [1] Parameters are shown [2] Parameters specified for [3] Latest of address valid, CS LOW, OE LOW, BLSx LOW (PB = 1). ...
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... NXP Semiconductors EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE EMC_Dx Fig 34. External static memory read/write access ( EMC_Ax EMC_CSx EMC_OE EMC_BLSx EMC_WE EMC_Dx Fig 35. External static memory burst read cycle Table 18. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits ...
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... NXP Semiconductors Table 18. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits pF amb Symbol Parameter t write valid delay time d(WV) t write hold time h(W) t output enable valid delay time d(GV) t output enable hold time h(G) t address valid delay time ...
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... NXP Semiconductors T cy(clk) EMC_CLKx t d(CS) EMC_DYCSx t d(RAS) EMC_RAS EMC_CAS EMC_WE EMC_DQMOUTx t d(A) EMC_Ax EMC_Dx Fig 36. Dynamic external memory interface signal timing (read access) 11.9 Ethernet Table 20. amb Symbol Parameter RMII mode f clk clk MII mode f clk clk t su ...
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... NXP Semiconductors Table 20. amb Symbol Parameter clk Output drivers can drive a load accommodating over 12 inch of PCB trace and the input [1] capacitance of the receiving device. [2] Timing values are given from the point at which the clock signal waveform crosses 1 the valid input or output level ...
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... NXP Semiconductors Fig 38. SD/MMC timing LPC4350_30_20_10 Objective data sheet 32-bit ARM Cortex-M4/M0 microcontroller T cy(clk) SD_CLK t d(QV) SD_CMD (O) SD_DATn (O) SD_CMD (I) SD_DATn (I) All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 23 September 2011 LPC4350/30/20/ su(D) h(D) 002aag204 © NXP B.V. 2011. All rights reserved. ...
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... NXP Semiconductors 12. ADC/DAC electrical characteristics Table 22. ADC characteristics V over specified ranges; T DDA(3V3) Symbol Parameter V analog input voltage IA C analog input capacitance ia E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G E absolute error T R voltage source interface ...
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... NXP Semiconductors 1023 1022 1021 1020 1019 1018 7 code out offset error E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (E (4) Integral non-linearity (E L(adj) (5) Center of a step of the actual transfer curve. (6) V refers pin VDDA and V ...
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... NXP Semiconductors Table 23. DAC electrical characteristics V over specified ranges; T DDA(3V3) Symbol Parameter E differential linearity error D E integral non-linearity L(adj) E offset error O E gain error G C load capacitance L R load resistance L LPC4350_30_20_10 Objective data sheet +85 C; unless otherwise specified ...
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... NXP Semiconductors 13. Application information 13.1 LCD panel signal usage Table 24. LCD panel connections for STN single panel mode External pin 4-bit mono STN single panel LPC43xx pin used LCD_VD[23:8] - LCD_VD7 - LCD_VD6 - LCD_VD5 - LCD_VD4 - LCD_VD3 P4_2 LCD_VD2 P4_3 LCD_VD1 P4_4 LCD_VD0 P4_1 ...
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... NXP Semiconductors Table 25. LCD panel connections for STN dual panel mode External pin 4-bit mono STN dual panel LPC43xx pin used LCD_VD2 P4_3 LCD_VD1 P4_4 LCD_VD0 P4_1 LCD_LP P7_6 LCD_ENAB/ P4_6 LCDM LCD_FP P4_5 LCD_DCLK P4_7 LCD_LE P7_0 LCD_PWR P7_7 GP_CLKIN PF_4 Table 26 ...
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... NXP Semiconductors Table 26. LCD panel connections for TFT panels External TFT 12 bit (4:4:4 pin mode) LPC43xx LCD pin used function LCD_VD0 - - LCD_LP P7_6 LCDLP LCD_ENAB P4_6 LCDENAB/ /LCDM LCDM LCD_FP P4_5 LCDFP LCD_DCLK P4_7 LCDDCLK LCD_LE P7_0 LCDLE LCD_PWR P7_7 LCDPWR ...
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... NXP Semiconductors Table 27. Fundamental oscillation frequency 12 MHz 16 MHz 20 MHz Table 28. Fundamental oscillation frequency 15 MHz 20 MHz Fig 40. Slave mode operation of the on-chip oscillator Fig 41. Oscillator modes with external crystal model used for C LPC4350_30_20_10 Objective data sheet Recommended values for C X1/X2 components parameters) low frequency mode ...
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... NXP Semiconductors 13.3 XTAL and RTCX Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors C third overtone crystal usage have a common ground plane. The external components must also be connected to the ground plain ...
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... NXP Semiconductors 14. Package outline LBGA256: plastic low profile ball grid array package; 256 balls; body ball A1 index area ball index area 2 4 DIMENSIONS (mm are the original dimensions) A UNIT max 0.45 1.1 0.55 mm 1.55 0.35 0.9 0.45 OUTLINE VERSION IEC SOT740 Fig 42. Package outline LBGA256 package ...
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... NXP Semiconductors TFBGA180: thin fine-pitch ball grid array package; 180 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) UNIT max 1.20 0.40 0.80 mm nom 1.06 0.35 0.71 min 0.95 0.30 0.65 OUTLINE VERSION IEC SOT570-3 Fig 43. Package outline of the TFBGA180 package ...
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... NXP Semiconductors LQFP208; plastic low profile quad flat package; 208 leads; body 1 156 157 pin 1 index 208 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 mm 1.2 0.3 0.65 0.4 OUTLINE VERSION IEC SOT926 Fig 45. Package outline of the TFBGA100 package ...
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... NXP Semiconductors LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... NXP Semiconductors LQFP100: plastic low profile quad flat package; 100 leads; body 1 pin 1 index 100 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors 15. Soldering Footprint information for reflow soldering of LBGA256 package P Hy solder land solder paste deposit solder land plus solder paste occupied area solder resist DIMENSIONS 1.00 0.450 0.450 0.600 17.500 17.500 Fig 48. Reflow soldering of the LBGA256 package LPC4350_30_20_10 Objective data sheet ...
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... NXP Semiconductors Footprint information for reflow soldering of TFBGA180 package P Hy solder land solder paste deposit solder land plus solder paste occupied area solder resist DIMENSIONS 0.80 0.400 0.400 0.550 12.575 12.575 Fig 49. Reflow soldering of the TFBGA180 package LPC4350_30_20_10 Objective data sheet ...
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... NXP Semiconductors Footprint information for reflow soldering of LQFP208 package solder land occupied area DIMENSIONS 0.500 0.560 31.300 31.300 28.300 28.300 Fig 50. Reflow soldering of the LQFP208 package LPC4350_30_20_10 Objective data sheet Hx Gx (0.125 (8× Generic footprint pattern Refer to the package outline drawing for actual layout ...
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... NXP Semiconductors Footprint information for reflow soldering of LQFP144 package solder land occupied area DIMENSIONS 0.500 0.560 23.300 23.300 20.300 20.300 Fig 51. Reflow soldering of the LQFP144 package LPC4350_30_20_10 Objective data sheet Hx Gx (0.125 (8× Generic footprint pattern Refer to the package outline drawing for actual layout ...
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... NXP Semiconductors Footprint information for reflow soldering of TFBGA100 package P Hy solder land solder paste deposit solder land plus solder paste occupied area solder resist DIMENSIONS 0.80 0.330 0.400 0.480 Fig 52. Reflow soldering of the TFBGA100 package LPC4350_30_20_10 Objective data sheet Hx P Generic footprint pattern ...
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... NXP Semiconductors Footprint information for reflow soldering of LQFP100 package solder land occupied area DIMENSIONS 0.500 0.560 17.300 17.300 14.300 14.300 Fig 53. Reflow soldering of the LQFP100 package LPC4350_30_20_10 Objective data sheet Hx Gx (0.125 (8× Generic footprint pattern Refer to the package outline drawing for actual layout ...
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... NXP Semiconductors 16. Abbreviations Table 29. Acronym ADC AES AHB APB API BOD CAN CMAC CSMA/CD DAC DC-DC DMA GPIO IRC IrDA JTAG LCD LSB MAC MCU MIIM n.c. OHCI OTG PHY PLL PMC PWM RIT RMII SDRAM SIMD SPI SSI SSP TCP/IP ...
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... NXP Semiconductors Table 29. Acronym USART USB UTMI LPC4350_30_20_10 Objective data sheet Abbreviations …continued Description Universal Synchronous Asynchronous Receiver/Transmitter Universal Serial Bus USB2.0 Transceiver Macrocell Interface All information provided in this document is subject to legal disclaimers. Rev. 2.1 — 23 September 2011 LPC4350/30/20/10 32-bit ARM Cortex-M4/M0 microcontroller © ...
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... NXP Semiconductors 17. Revision history Table 30. Revision history Document ID LPC4350_30_20_10 v.2.1 Modifications: LPC4350_30_20_10 v.2 LPC4350_30_20_10 v.1 LPC4350_30_20_10 Objective data sheet Release date Data sheet status 20110923 Objective data sheet • LQFP100 package added in • Pin P2_7 designated as ISP entry pin. • Boot pins corrected in P2_9 as boot pin ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... For sales office addresses, please send an email to: LPC4350_30_20_10 Objective data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 5 4.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 5 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 Functional description . . . . . . . . . . . . . . . . . . 65 7.1 Architectural overview . . . . . . . . . . . . . . . . . . 65 7.2 ARM Cortex-M4 processor . . . . . . . . . . . . . . . 65 7.3 ARM Cortex-M0 co-processor . . . . . . . . . . . . 65 7 ...
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... NXP Semiconductors 7.22.5 PLL0USB (for USB0 7.22.6 PLL0AUDIO (for audio 7.22.7 System PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.22.8 Reset Generation Unit (RGU 7.22.9 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.23 Serial Wire Debug/JTAG Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . 90 10 Static characteristics 10.1 Electrical pin characteristics . . . . . . . . . . . . . . 95 10.2 Power consumption . . . . . . . . . . . . . . . . . . . . 97 11 Dynamic characteristics . . . . . . . . . . . . . . . . 101 11 ...