STEVAL-IPE012V1 STMicroelectronics, STEVAL-IPE012V1 Datasheet - Page 15
STEVAL-IPE012V1
Manufacturer Part Number
STEVAL-IPE012V1
Description
EVAL BOARD ENERGY METER
Manufacturer
STMicroelectronics
Series
-r
Datasheets
1.STM8L151C4T6.pdf
(122 pages)
2.STEVAL-IPE012V1.pdf
(51 pages)
3.STEVAL-IPE012V1.pdf
(34 pages)
4.STEVAL-IPE012V1.pdf
(7 pages)
Specifications of STEVAL-IPE012V1
Design Resources
STEVAL-IPE012V1 Schematic STEVAL-IPE012V1 BOM
Main Purpose
Power Management, Energy/Power Meter
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
STPM10BTR, STM8L152
Primary Attributes
Single Phase with 1 Current Transformer & Shunt
Secondary Attributes
Tamper Detection
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
497-11462
- STM8L151C4T6 PDF datasheet
- STEVAL-IPE012V1 PDF datasheet #2
- STEVAL-IPE012V1 PDF datasheet #3
- STEVAL-IPE012V1 PDF datasheet #4
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- Download datasheet (2Mb)
STM8L151xx, STM8L152xx
3.2.2
Architecture and registers
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Addressing
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Instruction set
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Interrupt controller
The medium density STM8L15x features a nested vectored interrupt controller:
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Harvard architecture
3-stage pipeline
32-bit wide program memory bus - single cycle fetching most instructions
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
8-bit accumulator
24-bit program counter - 16 Mbyte linear memory space
16-bit stack pointer - access to a 64 Kbyte level stack
8-bit condition code register - 7 condition flags for the result of the last instruction
20 addressing modes
Indexed indirect addressing mode for lookup tables located anywhere in the address
space
Stack pointer relative addressing mode for local variables and parameter passing
80 instructions with 2-byte average instruction size
Standard data movement and logic/arithmetic functions
8-bit by 8-bit multiplication
16-bit by 8-bit and 16-bit by 16-bit division
Bit manipulation
Data transfer between stack and accumulator (push/pop) with direct stack access
Data transfer using the X and Y registers or direct memory-to-memory transfers
Nested interrupts with 3 software priority levels
32 interrupt vectors with hardware priority
Up to 40 external interrupt sources on 11 vectors
Trap and reset interrupts
Doc ID 15962 Rev 6
Functional overview
15/122
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