AM186CC-50KD\W C AMD (ADVANCED MICRO DEVICES), AM186CC-50KD\W C Datasheet - Page 34

• Manufacturer Part Number: AM186CC-50KD\W C
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM186CC-50KD\W C

• Lead Free Status / Rohs Status: Compliant

Figure 4 on page 36 shows a bus cycle when address
bus disable is in effect, which causes the AD bus to
operate in a nonmultiplexed data-only mode. The A bus
has the address during a read or write operation.
Bus Interface Unit
The bus interface unit controls all accesses to external
peripherals and memory devices. External accesses include
those to memory devices, as well as those to memory-
mapped and I/O-mapped peripherals and the peripheral
control block. The Am186CC microcontroller provides an
enhanced bus interface unit with the following features:
n Nonmultiplexed address bus
n Separate byte write enables for high and low bytes
n Output enable
The standard 80C186/80C188 multiplexed address
and data bus requires system interface logic and an ex-
ternal address latch. On the Am186CC microcontroller,
byte write enables and a nonmultiplexed address bus
can reduce design costs by eliminating this external
logic.
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19–A0) is valid one-
half CLKOUT cycle in advance of the address on the
AD bus. When used in conjunction with the modified
UCS and LCS outputs and the byte write enable
signals, the A19–A0 bus provides a seamless interface
to exter nal SRAM, and Flash memor y/EPROM
systems.
Byte Write Enables
The Am186CC microcontroller provides the WHB
(Write High Byte) and WLB (Write Low Byte) signals
that act as byte write enables.
WHB is the logical OR of BHE and WR. WHB is Low
when both BHE and WR are Low. WLB is the logical
OR of A0 and WR. WLB is Low when A0 and WR are
both Low.
T h e b y t e w r i t e e n a b l e s a r e d r i ve n w i t h t h e
nonmultiplexed address bus as required for the write
timing requirements of common SRAMs.
Output Enable
The Am186CC microcontroller provides the RD (Read)
signal which acts as an output enable for memory or
peripheral devices. The RD signal is Low when a word
or byte is read by the Am186CC microcontroller.
DRAM Support
To support DRAM, the Am186CC microcontroller has a
fully integrated DRAM controller that provides a glueless
interface to 25–70-ns Extended Data Out (EDO) DRAM.
(EDO DRAM is sometimes called Hyper-Page Mode
DRAM.) Up to two banks of 4-Mbit (256 Kbit x 16 bit)
DRAM can be accessed. Page Mode DRAM, Fast Page
34
Am186™CC Communications Controller Data Sheet
Mode DRAM, Asymmetrical DRAM, and 8-bit wide
D R A M a r e n o t s u p p o r t e d . T h e A m 1 8 6 C C
microcontroller includes a glueless DRAM interface
providing zero-wait state operation at up to 50 MHz with
40-ns DRAM. This allows designs requiring larger
amounts of memory to save system cost over SRAM
designs by taking advantage of low DRAM memory
costs.
The DRAM interface uses various chip select pins to
implement the RAS/CAS interface required by DRAMs.
The Am186CC DRAM controller drives the RAS/CAS
interface appropriately during both normal memory
accesses and during refresh. All signals required are
generated by the Am186CC microcontroller and no
external logic is required.
The DRAM multiplexed address pins are connected to
the Am186CC microcontroller’s odd address pins,
starting with A1 on the Am186CC microcontroller
connecting to MA0 on the DRAM. The correct row and
column addresses are generated on these odd
address pins during a DRAM access.
The RAS pins are multiplexed with LCS and MCS3,
allowing a DRAM bank to be present in either high or
low memory space. The MCS2 and MCS1 function as
the upper and lower CAS pins, respectively, and define
which byte of data in a 16-bit DRAM is being accessed.
The Am186CC microcontroller supports the most
common DRAM refresh option, CAS-Before-RAS. All
refresh cycles contain three wait states to support the
DRAMs at various frequencies. The DRAM controller
never performs a burst access. All accesses are single
accesses to DRAM. If the PCS chip selects are
decoded to be in the DRAM address range, PCS
accesses take precedence over the DRAM.
Chip Selects
The Am186CC microcontroller provides six chip select
outputs for use with memory devices and eight more
for use with peripherals in either memory or I/O space.
The six memory chip selects can be used to address
three memory ranges. Each peripheral chip select
a d d r e s s e s a 2 5 6 - b y t e b l o c k o f f s e t f r o m a
programmable base address.
The Am186CC microcontroller can be programmed to
sense a ready signal for each of the peripheral or
memory chip select lines. A bit in each chip select
control register determines whether the external ready
signal is required or ignored.
The chip selects can control the number of wait states
inserted in the bus cycle. Although most memory and
peripheral devices can be accessed with three or less
wait states, some slower devices cannot. This feature
allows devices to use wait states to slow down the bus.